| Wirelessly Networked Digital Phased Array: Design and Analysis of a 2.4 GHz Demonstrator |
SEP 2006 |
128 pages |
| Authors:
Gert Burgstaller; NAVAL POSTGRADUATE SCHOOL MONTEREY CA DEPT OF ELECTRICAL AND COMPUTER ENGINEERING
|
 | The wirelessly networked opportunistic digital array radar (WNODAR) system combines opportunistic phased array and aperstructure concepts. The array elements contain stand alone transmit receive (T/R) modules with no hardwire connections other than prime power and are wirelessly networked to a central controller and processor unit. A full scale WNODAR operating in the VHF/UHF frequency bands (300 MHz) exhibits many favorable properties, which make the system suitable for ballistic missile defense ... |
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| Radiation Testing of the Configurable Fault Tolerant Processor (CFTP) for Space-Based Applications |
DEC 2005 |
165 pages |
| Authors:
James C. Coudeyras; NAVAL POSTGRADUATE SCHOOL MONTEREY CA DEPT OF ELECTRICAL AND COMPUTER ENGINEERING
|
| Field Programmable Gate Arrays (FPGAs) provide a reconfigurable asset in the design of space computing. Hardware configurations are stored in FPGA memory elements, which are susceptible to Single Event Upsets (SEUs). What is the best way to detect and mitigate SEUs and correct them before they become functional errors? The Configurable Fault Tolerant Processor (CFTP) consists of a controller FPGA (X1) controlling an experiment FPGA (X2), which can be used ... |
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| Implementation of a Fault Tolerant Processor (CFTP) Using Internal Triple Modular Redundancy (TMR) |
DEC 2005 |
109 pages |
| Authors:
Peter J. Majewicz; NAVAL POSTGRADUATE SCHOOL MONTEREY CA
|
| The environment of space is challenging to digital equipment due to the interaction between electrical systems and the radiation of space. One such effect is the Single Event Upset (SEU), which occurs when radiation causes a logical bit value to change. These effects are magnified in reconfigurable digital systems that utilize Field Programmable Gate Arrays (FPGA) because both the configuration and the data are susceptible to SEUs. Several techniques have ... |
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| Integrated Chemical Fuel Microprocessor for Power Generation in MEMS Applications |
24 AUG 2005 |
40 pages |
| Authors:
Klavs F. Jensen; MASSACHUSETTS INST OF TECH CAMBRIDGE DEPT OF CHEMICAL ENGINEERING
|
| This document reports results obtained via Integrated Chemical Fuel Microprocessor for Power Generation in MEMS Applications" during the performance period, 1 September 1999 - 31 March 2004. The overall goal of this program was to demonstrate a chemical fuel processing microsystem for power generation in MEMS applications. The program had several major accomplishments: 1. Development and fabrication of a new, thermally efficient, suspended tube MEMS heat exchanger/fuel processor. 2. Design ... |
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| Scalable Shared Memory Supercomputer Replacement for DOD Research |
08 AUG 2005 |
32 pages |
| Authors:
J. V. Moloney; ARIZONA UNIV TUCSON DEPT OF MATHEMATICS
|
| This instrumentation grant has enabled a dramatic enhancement in in-house supercomputing power at ACMS. The SGI ONXY2 22-processor system with 7 Gbytes of memory was replaced by the new SGI Altix 32-Itanium processor system with 64 Gbytes of memory. The combination of higher speed process (factor of 6), higher interprocessor bandwidth and much larger accessible shared memory (64 Gbytes) has meant that problems that were previously inaccessible are now well ... |
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| Prognostics Models of Combat Vehicles Software |
05 JUN 2005 |
18 pages |
| Authors:
Elena Bankowski; Abul Masrur; TACOM RESEARCH DEVELOPMENT AND ENGINEERING CENTER WARREN MI
|
| The Next Generation Software and Survivability Technology areas of TARDEC RDECOM proposed the Dependable Automated Reconfigurable Technology (DART). The DART's "Health & Situation Control" will test the processing elements with Probe/Agent technology for software checking. Algorithms within the Health & Situation Control will assess the health of the processors and recommend element hand-off based on a "Criticality Scoring System" in conjunction with the Statistical Usage Test (SUT) model. The DART ... |
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| Microarchitectural Floorplanning for Thermal Management: A Technical Report |
20 MAY 2005 |
12 pages |
| Authors:
Karthik Sankaranarayanan; Sivakumar Velusamy; Kevin Skadron; Mircea Stan; VIRGINIA UNIV CHARLOTTESVILLE DEPT OF COMPUTER SCIENCE
|
| In current day microprocessors, exponentially increasing power densities, leakage, cooling costs, and reliability concerns have resulted in temperature becoming a first class design constraint like performance and power. Hence, virtually every high performance microprocessor uses a combination of an elaborate thermal package and some form of Dynamic Thermal Management (DTM) scheme that adaptively controls its temperature. While DTM schemes exploit the important variable of power density to control temperature, this ... |
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| Model-Based Integrated Simulation (MILAN) |
MAR 2005 |
35 pages |
| Authors:
Viktor K. Prasanna; Cauligi S. Raghavendra; Akos Ledeczi; UNIVERSITY OF SOUTHERN CALIFORNIA LOS ANGELES
|
| The motivation for the Model-based Integrated Simulation (MILAN) project is to develop an extensible modeling, simulation, and design space exploration framework for the design of latency and energy efficient embedded systems for signal processing applications. Design of embedded systems requires minimization of energy dissipation (to maximize battery life) while meeting a given latency constraint (typically real-time constraints). While until now Application Specific Integrated Circuits (ASICs) were considered the primary choice ... |
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| Initial Kernel Timing Using a Simple PIM Performance Model |
01 FEB 2005 |
29 pages |
| Authors:
Daniel S. Katz; Gary L. Block; Paul L. Springer; Thomas Sterling; Jay B. Brockman; David Callahan; JET PROPULSION LAB PASADENA CA
|
| This presentation will describe some initial results of paper-and- pencil studies of 4 or 5 application kernels applied to a processor-in-memory (PIM) system roughly similar to the Cascade Lightweight Processor (LWP). The application kernels are: * Linked list traversal * Sun of leaf nodes on a tree * Bitonic sort * Vector sum * Gaussian elimination The intent of this work is to guide and validate work on the Cascade ... |
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| Load Latency Tolerance in Dynamically Scheduled Processors |
2005 |
13 pages |
| Authors:
Srikanth T. Srinivasan; Alvin R. Lebeck; DUKE UNIV DURHAM NC DEPT OF COMPUTER SCIENCE
|
| This paper provides quantitative measurements of load latency tolerance in a dynamically scheduled processor. To determine the latency tolerance of each memory load operation, our simulations use flexible load completion policies instead of a fixed memory hierarchy that dictates the latency. Although our policies delay load completion as long as possible, they produce performance (instructions committed per cycle (IPC)) comparable to an ideal memory system where all loads complete in ... |
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| Logistic Fuel Processor Development |
JAN 2004 |
28 pages |
| Authors:
Reza Salavani; Aly H. Shaaban; Timothy Campbell; Mikel Sawyer; Richard Trotta; AIR FORCE RESEARCH LAB TYNDALL AFB FL MATERIALS AND MANUFACTURING DIRECTORATE
|
| The Air Base Technologies Division of the Air Force Research Laboratory has developed a logistic fuel processor that removes the sulfur content of the fuel and in the process converts logistic fuel to light gases then steam reform the light gases into hydrogen rich stream. This report documents the efforts in developing a fuel processor capable of providing hydrogen to a 3kW fuel cell stack. The technical challenges in the ... |
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| JP-8 Catalytic Cracking for Compact Fuel Processors |
2004 |
10 pages |
| Authors:
Timothy J. Campbell; Aly H. Shaaban; Franklin H. Holcomb; Reza Salavani; Michael J. Binder; AIR FORCE RESEARCH LAB TYNDALL AFB FL
|
| In processing heavier hydrocarbons such as military logistic fuels (JP-4, JP-5, JP-8 and JP-100), kerosene, and diesel to produce hydrogen for fuel cell use, several issues arise. First, these fuels have high sulfur content, which can poison and deactivate components of the reforming process and the fuel cell stack; second, these fuels may contain non-volatile residue (NVR), up to 1. 5 vol. %, which could potentially accumulate in a fuel ... |
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| Data Intensive Systems (DIS) Benchmark Performance Summary |
AUG 2003 |
144 pages |
| Authors:
Joseph Musmanno; TITAN SYSTEMS CORP WALTHAM MA
|
| Peak processor performance increases at a rate of 60% per year, but memory access speeds increase at a rate of only 7% per year. Computing-system designers compensate for the resulting divergence by incorporating caches or latency-hiding measures into their designs. However, elements such as larger caches, prefetching, and multithreading do not address the needs of data- intensive DoD applications, which consequently operate at rates far below the peak processor- capacity. ... |
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| Radiation Tolerant Embedded Memory |
19 JUN 2003 |
26 pages |
| Authors:
Brian Smith; Greg Alkire; PICODYNE CORP ANNAPOLIS MD
|
| Report Developed under SBIR contract for topic MDA02-021. PicoDyne has developed Ultra-Low-Power(ULP) CMOS design techniques and processes, and combined them with Radiation Hardened By Design methodologies to form its Cool- RAD(tm) process. Complex ULP and Cool- RAD(tm) parts have been built, including data compression devices, Reed-Solomon Encoders and Decoders, and digital signal processors. Memory blocks have been embedded in ULP chips. Radiation Tolerant Memory presents new challenges to the chip ... |
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| CILK: A Multi-Threaded Programming System for Meta-Computers |
DEC 2001 |
47 pages |
| Authors:
Lawrence Snyder; MASSACHUSETTS INST OF TECH CAMBRIDGE LAB FOR COMPUTER SCIENCE
|
| Contracts F30602-97-l-0150 and F306O2-97-l-0270 were a joint effort but funded using different contract vehicles at the request of DARPA, the sponsoring agency. This report documents the design and development of CILK, a language for multi-threaded parallel programming based on ANSI C. CILK is designed for genera-purpose parallel programming, but it is especially effective for exploiting dynamic, highly asynchronous parallelism, which can be difficult to write in data-parallel or message-passing style. ... |
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| Implementation of a Fault Tolerant Computing Testbed: A Tool for the Analysis of Hardware and Software Fault Handling Techniques |
JUN 2000 |
185 pages |
| Authors:
David C. Summers; NAVAL POSTGRADUATE SCHOOL MONTEREY CA
|
| With spacecraft designs placing more emphasis on reduced cost, faster design time, and higher performance, it is easy to understand why more commercial-off-the-shelf (COTS) devices are being used in space based applications. The COTS devices offer spacecraft designers shorter design-to- orbit times, lower system costs, orders of magnitude better performance, and a much better software availability than their radiation hardened (radhard) counterparts. The major ... |
|
| Embedded Genetic Allocator |
JAN 2000 |
46 pages |
| Authors:
David B. Cousins; Fred Roeber; BBN TECHNOLOGIES CAMBRIDGE MA
|
| This final report documents the work accomplished under the Embedded Genetic Allocator Program, a two year effort funded by DARPA/ITO. The major accomplishment of the program was to develop a new approach to the problem of automatically optimizing the use of memory and processor resources in high performance computing systems consisting of heterogeneous processor nodes connected on a high-speed interconnection fabric. This is frequently known ... |
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| Waste Aerosol Container Processor |
19 OCT 1999 |
|
| Authors:
David L. Dummer; Jack L. McCrea; Roy J. Maloney; DEPARTMENT OF THE NAVY WASHINGTON DC
|
 | The invention features implementation of a flat triangular blade which has two cutting edges and a sharp point. The blade is caused to move point wise across a cylindrical can's diameter, with the plane of the blade perpendicular to the can's axis, so that the point pierces the can, the two cutting edges slice through the can in both directions around the can's circumference, and the point again, diametrically oppositely, ... |
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| Graphics Equipment for Real Time Animation and Virtual Design of Electronic Materials Processes |
MAY 1999 |
3 pages |
| Authors:
Vishwanath Prasad; Hui Zhang; STATE UNIV OF NEW YORK AT STONY BROOK
|
| The Objective of this research equipment grant was to purchase computing equipment to upscale the local graphics infrastructure and to accomplish successfully the research tasks of AFOSR/DARPA MURI project on "Integrated, Intelligent Modeling, Design and Control of Crystal Growth Processes." As proposed, Silicon Graphics Onyx 2 Infinite Reality Graphics Rack System has been purchased and networked with other computers in the Process Modeling Laboratory. This computer has greatly enhanced the ... |
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| Apparel Research Network (ARN). Apparel Order Processing Module (AOPM) Interfaced with The Electronic Order Form (EOF) (AOPM/EOF) |
29 APR 1999 |
11 pages |
| Authors:
Denise Carley; EDI INTEGRATION CORP CROFTON MD
|
| The ARN AOPM Application System was developed to retrieve and processspecial measurement and stock orders for military clothing. AOPM was initially developed to replace the SF 358 and SF 1111, the special measurement forms used for male and female personnel. After completion of AOPM, ARN Partner Clemson Apparel Research (CAR), initiated the Electronic Order Form (EOF) Project. The purpose of the EOF Project was to place the special measurement ordering ... |
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| Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing |
1999 |
11 pages |
| Authors:
Paul Graham; Brent Nelson; BRIGHAM YOUNG UNIV PROVO UT
|
| For high-performance, embedded digital signal processing, digital signal processors (DSPs) are very important. Further, they have many features which make their integration with on-chip reconfigurable logic (RL) resources feasible and beneficial. In this paper, we discuss how this integration might be done and the potential area costs and performance benefits of incorporating RL onto a DSP chip. For or proposed architecture, a reconfigurable coprocessor can provide speed-ups ranging from 2-32x ... |
|
| VEIL: Research in Knowledge Representation for Computer Vision |
FEB 1998 |
74 pages |
| Authors:
Thomas A. Russ; Keith Price; Robert B. MacGregor; Ram Nevatia; Behnam Salemi; UNIVERSITY OF SOUTHERN CALIFORNIA MARINA DEL REY INFORMATION SCIENCES INST
|
| The VEIL (Vision Environment Integrating Loom) project integrated advanced Knowledge Representation (KR) technology (Loom) with image understanding technology. The major innovations are as follows: 1) Use of declarative knowledge (as opposed to procedural knowledge) in vision systems made extending the recognition capabilities of the software easier. 2) Facilitated integrating high-level vision routines (recognizing sequences of scenes) with low-level routines that recognize picture elements. ... |
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| Improved Methods for Regionalized Surface Wave Analysis |
SEP 1997 |
68 pages |
| Authors:
J. L. Stevens; K. L. McLaughlin; MAXWELL TECHNOLOGIES INC SAN DIEGO CA
|
| We develop optimized methods for measuring surface waves for event screening under a CTBT. The optimization techniques are: a regionalized earth model, phase-matched filtering, path corrected surface wave spectral magnitude; maximum likelihood magnitudes and upper bounds. A regionalized earth model is developed by tomographic inversion of surface wave data starting with the Crust 5.1 earth models, and using dispersion measurements from PIDC data, historic explosion data, and data sets from ... |
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| Method for Processing Contaminated Plastic Waste. |
02 MAY 1995 |
|
| Authors:
Peter S. McGraw; John L. Drake Jr; Thomas H. Hane; DEPARTMENT OF THE NAVY WASHINGTON DC
|
| A compress/melt waste processor includes a frame; a chamber housing having walls which define a chamber therein; a ram movably disposed in the chamber; a sensor which senses pressure applied by the ram; an actuator operatively connected to the ram to move the ram; a chamber hatch upon which the housing is mounted, the chamber housing walls, the ram and the chamber hatch defining a space there between; and a ... |
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| Semiconductor Process Synthesis. Virtual Reactor and Recipe Synthesis Frameworks for Rapid Equipment and Process Development |
02 APR 95 |
33 pages |
| Authors:
Mehrdad M. Moslehi; CVC PRODUCTS INC FREMONT CA
|
| In this Phase I program, we developed modules and strategy for a Virtual Reactor (VR) Framework and a recipe Synthesizer (RS) Framework for single-wafer thermal processing equipment. These frameworks constitute components of the Unit Process & Module Synthesis System. This system enables equipment and process engineers to quickly design fabrication equipment and synthesize unit processes and modules in response to requirements generated by the flow synthesis framework. The first step ... |
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| Defense Support Program: Ground Station Upgrades Not Based on Validated Requirements |
21 MAY 93 |
6 pages |
| Authors:
GENERAL ACCOUNTING OFFICE WASHINGTON DC NATIONAL SECURITY AND INTERNATIONAL A FFAIRS DIV
|
| This report summarizes our review of whether planned upgrades costing up to $95 million to Defense Support Program (DSP) ground processing stations are supported by validated operational requirements. DSP is a strategic surveillance and early warning satellite system. It is premature to upgrade DSP ground stations because the Air Force has not completed validation of operational requirements as required by Department of Defense (DOD) Instruction 5000.2 and Air Force Regulation ... |
|
| Reconfiguration Schemes for Fault-Tolerant Processor Arrays |
15 OCT 92 |
216 pages |
| Authors:
Jose A. Fortes; PURDUE UNIV LAFAYETTE IN
|
| This project addressed several aspects of the problem of designing highly-reliable dynamically reconfigurable processor arrays. The proposed work focused mainly on reconfiguration schemes required to implement fault-tolerant processor arrays. According to the original statement of work, the following complementary objectives were pursued: (1) a methodology for the design and evaluation of processor-switched arrays. (2) a methodology for the design and evaluation of multi-level hierarchically reconfigurable processor arrays. (3) a methodology ... |
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| Rapid Prototyping of Application Specific Signal Processors (RASSP) program - Study Phase |
12 OCT 92 |
150 pages |
| Authors:
Fred Malver; Andrzej Peczalski; Wing Au; Jonathon Krueger; David Lee; HONEYWELL SYSTEMS AND RESEARCH CENTER BLOOMINGTON MN
|
| This is the final report for the Rapid Prototyping of Applications Specific Signal Processors (RASSP) Program - Study Phase. This study represents a five-month contract effort, DARPA contract number MDA972-92-C-0057, performed by Honeywell's Systems and Research Center for the Defense Advanced Research Projects Agency, DARPA. The Broad objective of this study was to produce information that would aid the Government program manager to manage the risks inherent in the implementation ... |
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| Rapid Prototyping of Application Specific Signal Processors (RASSP) |
09 OCT 92 |
126 pages |
| Authors:
George J. Agule; Stephen M. Lorusso; Kelley J. Arsenault; Paul N. Bompastore; Robert V. Bryant; RAYTHEON CO TEWKSBURY MA MISSILE SYSTEMS DIV
|
| The report is organized to provide information to program managers in support of their efforts to manage the risks inherent in the Implementation Phase of the RASSP program. This document is a compendium of study phase reports that together form a comprehensive reference useful for gaining insight into the complexities and feasibility of developing application specific signal processors that meet MODEL YEAR cost, schedule, and upgrade objectives. Design System, Interoperability, ... |
|
| Hartstone Benchmark Results and Analysis |
JUN 90 |
|
| Authors:
Patrick Donohue; Ruth Shapiro; Nelson Weiderman; CARNEGIE-MELLON UNIV PITTSBURGH PA SOFTWARE ENGINEERING INST
|
| Hartstone is a series of timing requirements for testing a system's ability to handle hard real-time applications. It is specified as a set of processes with well-defined workloads and timing constraints. The name Hartstone derives from Hard Real Time and the fact the workloads are based on the well- known Whetstone benchmark. This report describes the results obtained by running Version 1.0 of the Hartstone benchmark, an Ada implementation of ... |
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| Approaches to the Processing of Data from Large Aperture Acoustic Vertical Line Arrays |
APR 90 |
137 pages |
| Authors:
Jean-Marie Q. Tran; SCRIPPS INSTITUTION OF OCEANOGRAPHY LA JOLLA CA MARINE PHYSICAL LAB
|
| This dissertation investigates various approaches to the processing of narrowband frequency data from large aperture acoustic vertical line arrays with on the order of one hundred equally spaced sensors. When little is known about the oceanic environment, beamforming is performed to detect signals and estimate the vertical arrival structure of the pressure field. The attention is focussed on using the adaptive Minimum Variance processor. The issues of signal cancellation due ... |
|
| Hardware-In-The-Loop Testing of KEW Flight Processors |
16 MAR 1990 |
74 pages |
| Authors:
C. O. Alford; R. T. Abler; W. S. Tan; A. H. Register; GEORGIA INST OF TECH ATLANTA COMPUTER ENGINEERING RESEARCH LAB
|
| The Computer Engineering Research Laboratory at the Georgia Institute of Technology, under contract to the United States Army Strategic Defense Command, is developing special purpose parallel computers for hardware-in-the- loop simulation and testing of kinetic energy weapons (KEW) systems and components. Of primary interest is the ability to test guidance, navigation and control (GN&C) algorithms. This paper presents details on a hardware-in-the-loop test of a Honeywell (Sandia) S5, GN&C processor. ... |
|
| An Introduction to the Information Processing Components of the Brain |
12 JAN 90 |
25 pages |
| Authors:
S. Collins; ROYAL SIGNALS AND RADAR ESTABLISHMENT MALVERN (UNITED KINGDOM)
|
| Over the past decade there has been increasing interest in neurological inspired computational techniques. This interest arises from the concurrence of two factors; firstly, a growing list of interesting tasks for which serial digital computers are unsuitable, and secondly, information gained from the application of new techniques in neurobiology. This text is intended to provide an introduction to neurobiological terms of physical scientists and engineers, with some pointers to further ... |
|
| Multiprocessor Realization of Neural Networks |
90 |
348 pages |
| Authors:
Robert W. Bennington; AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH
|
| This research provides a foundation for implementing neural networks on multiprocessor systems in order to increase execution speeds and to accommodate more complex neural networks. The emphasis is on the use of affordable coarse grain multiprocessors to implement commercially available neural network simulators currently being run on single processor systems. A conceptual framework is presented based on the concepts of program decomposition, load balancing, communication overhead, and process synchronization. Four ... |
|
| An Intelligent Job Dispatcher for Computer Systems |
22 DEC 89 |
15 pages |
| Authors:
Jurn S. Leung; GENERAL PURPOSE MACHINES LAB IRVINE CA
|
| The Intelligent Job Dispatcher has two networks, the LMN-net and the information gathering network. The main result of this effort is the architecture of the LMN-net, which optimizes the assignment of N jobs to M processors in a window of L time steps. Input to this network are information on job loads, processor capacities, and inter-job dependence. Output of this network are assignment matrices. This network is a modified Hopfield ... |
|
| Simulation and Mixed Integer Linear Programming Models for Analysis of Semi-Automated Mail Processing |
DEC 89 |
215 pages |
| Authors:
Steven D. Wert; AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH
|
| Over the last decade, much attention has been focused on the development of automated letter mail processing systems for postal sorting. Optical character readers and bar-code sorters have begun to augment mechanized processing that has been in use since the mid-1960s. Continuing automated mail processing programs are aimed at minimizing growth in labor costs, which at $30. 5 billion accounted for 83 percent of the total United States Postal Service ... |
|
| Testing and Data Path Redesign of a High Speed, 16-Point Winograd Fourier Transform Processor |
DEC 89 |
139 pages |
| Authors:
Steven W. Pavick; AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH SCHOOL OF ENGINEERING
|
| A prototype 16-point, 70 MHz Fourier transform processor using 1.2 micron minimum feature sizes was tested using a Tektronix DAS 9200, digital analysis system. The results showed that it is possible to operate an Air Force Institute of Technology (AFIT) WFT16 chip at 70 MHz. The results also showed a great deal of variation among the individual packaged chips. Using the WFT16's built in testing circuitry, portions of the main ... |
|
| A Distributed Kernel for Simulation of the VHSIC Hardware Description Language |
DEC 89 |
124 pages |
| Authors:
Michael C. Proicou; AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH SCHOOL OF ENGINEERING
|
| This thesis develops a technique for simulating large-scale circuit models, written in the Very High Speed Integrated circuit Hardware Description Language (VHDL), on a distributed computer composed of many individual processing units. The distributed system consists of a scalable kernel which can support a large simulation composed of many concurrent VHDL processes. The kernel provides model-independent support functions that handle signal propagation and process activation in a distributed environment. The ... |
|
| Technology Development and Circuit Design for a Parallel Laser Programmable Floating Point Application Specific Processor |
DEC 89 |
123 pages |
| Authors:
Michael W. Scriber; AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH SCHOOL OF ENGINEERING
|
| The laser programmable floating point application specific processor (LPASP) is a new approach at rapid development of custom VLSI chips. The LPASP is a generic application specific processor that can be programmed to perform a specific function. The effort of this thesis is to develop and test the double precision floating point adder and the laser programmable read-only memory (LPROM) that are macrocells within the LPASP. In addition, the thesis ... |
|
| Radiation-Hardened Wafer Scale Integration |
25 OCT 89 |
|
| Authors:
A. H. Anderson; J. A. Burns; C. K. Chen; G. J. Dunn; K. H. Konkle; MASSACHUSETTS INST OF TECH LEXINGTON LINCOLN LAB
|
| This report describes the logical and physical design of a prototype focal plane processor to be built as a wafer-scale circuit in a radiation-hard CMOS process. Design details and test results are presented for the five circuits which were fabricated in bulk CMOS through the MOSIS fabrication service. The floor plan of the wafer is described. This project was terminated before the wafer-scale circuit could be fabricated. New methods and ... |
|
| Ultra High Performance, Highly Reliable, Numeric Intensive Processors and Systems |
OCT 89 |
36 pages |
| Authors:
Fred J. Taylor; FLORIDA UNIV GAINESVILLE DEPT OF ELECTRICAL ENGINEERING
|
| Arithmetic bandwidth remains one of the principal bottlenecks in real-time-high-end signal, image, and data processing applications. The problem is compounded when complex arithmetic is required. The problem, unfortunately, does not stop there. For military applications, size (volume) and power dissipation often are as important as bandwidth. Unfortunately speed and complexity (size-power) metrics are often in conflict. As a result, the defense signal processing systems designer finds that performance requirements often ... |
|
| Critical Problems in Very Large Scale Computer Systems |
30 SEP 89 |
|
| Authors:
Anant Agarwal; William J. Dally; Srinivas Devadas; Thomas F. Knight Jr.; F. T. Leighton; MASSACHUSETTS INST OF TECH CAMBRIDGE
|
| The research vehicle for this contract is the largest possible computer that could be conceived for the mid to late 1990's. The technical challenges of such a machine serve as our guiding stimulus for the research carried out and reported here. We imagine this machine to occupy a 14-story building, to cost upward of $1 billion, and to be so colossal that the nation could only afford one or two ... |
|
| Voice Preprocessor for Digital Voice Applications |
11 SEP 89 |
41 pages |
| Authors:
G. S. Kang; L. J. Fransen; T. M. Moran; NAVAL RESEARCH LAB WASHINGTON DC
|
| A voice processor operating satisfactorily in laboratory environments with carefully prerecorded speech samples often fails to operate satisfactorily with live speech. Potential reasons are: (1) the speech level may be too high or too low; (2) the speech signal may have too much interference (ambient noise, breath noise, 60 Hz hum, digital noise in analog circuits, a DC bias (caused by component aging, etc.) generated at the analog-to-digital converter output); ... |
|
| Adaptive Associative-Processing Optical Computing Architectures. |
29 AUG 1989 |
|
| Authors:
Arthur D. Fisher; DEPARTMENT OF THE NAVY WASHINGTON DC
|
| Accordingly, one object of the present invention is to provide a novel associative processing module which adapts in real-time as it is exposed to associated information patterns, so, at a later time presentation of one pattern results in recall of the other. Another object of the present invention is to provide a novel associative processing module which adaptively learns in real-time, even while simultaneously recalling associations. Another object of the ... |
|
| Broadband Sonar Signal Processor and Target Recognition System. |
11 JUL 1989 |
|
| Authors:
Whitlow W. Au; Douglas W. Martin; DEPARTMENT OF THE NAVY WASHINGTON DC
|
| Target discrimination involves processing of sonar echoes in the time-domain and using features of the targets that the human auditory system uses (time separation and amplitude of echo highlights). Known targets are placed in the water and ensonified by multiple broadband transient signals. Echoes from each of the known targets have time-domain feature data extracted and stored to construct a library of known target features. Unknown targets echoes of transmitted ... |
|
| Distribution of Processing Tasks for the REMIDS II Real-Time Processor System |
01 JUN 89 |
9 pages |
| Authors:
R. Horner; ENVIRONMENTAL RESEARCH INST OF MICHIGAN ANN ARBOR
|
| The demonstration system must perform many different operations to successfully locate minefields in real time. These operations fall into the categories of: Scanner data input, Scanner data processing, Inter-processor communication, and Display data output. The time-line also provides an overall view of the operations from which system-level requirements may be derived. For instance it shows three parallel processes occuring concurrently on the DAP-610. Support of this concurrent processing from AMT ... |
|
| The NOSC (Naval Ocean Systems Center) Code 911 Digital Dynamics Processor (DDP). A Mildly Coupled Distributed-Computing System |
MAY 89 |
14 pages |
| Authors:
S. P. Murphy; NAVAL OCEAN SYSTEMS CENTER SAN DIEGO CA
|
| This paper describes the Naval Ocean Systems Center (NOSC), Code 911 Digital Dynamics Processor (DDP). The DDP is a multiprocessor system designed for high speed numerical calculation. This system implements a new variation of common memory in order to allow a far greater number of processors than found currently on a TCDS. The conceptual design of the DDP was done in mid and late 1984 by Jack Zyphur. A variation ... |
|
| Three Dimensional Cellular Automata for Subpixel Target Detection |
15 MAR 89 |
69 pages |
| Authors:
Kendall Preston Jr; KENSAL CONSULTING TUCSON AZ
|
| This project on subpixel target detection relates to research in the optimization of three-dimensional computing structures for use in target detection and to research in the reduction of an optimum computing to an efficiently-designed silicon chip. The work reported here has led to this final report which is divided into three sections: (1) presentation of the mathematical analysis which treats multiply-redundant massively-parallel processors for target detection, (2) a report on ... |
|
| Three Dimensional Cellular Automata for Subpixel Target Detection |
10 MAR 89 |
18 pages |
| Authors:
Kendall Preston Jr; KENSAL CONSULTING TUCSON AZ
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| This project on subpixel target detection relates to research in the optimization of three-dimensional computing structures for use in target detection and to research in the reduction of an optimum computing to an efficiently-designed silicon chip. During the work period reported here research continued on the mathematical optimization of optimizing the device design assuming a planar geometry has been completed. There are well-defined optima which had not heretofore been recognized. ... |
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| Time Code Formats |
MAR 89 |
46 pages |
| Authors:
RANGE COMMANDERS COUNCIL WHITE SANDS MISSILE RANGE NM INTER- RANGE INSTRUMENTAT ION GROUP
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| Modern day electronic systems such as communication systems, data handling systems, missile and spacecraft tracking, and telemetry systems require time-of-day information for data correlation with time. Parallel and serial formatted time codes are used to efficiently interface the timing system (time- of-day source) to the user system. Parallel time codes are defined in IRIG standard 205-87. Standardization of time codes is necessary to ensure system compatibility among the various ranges, ... |
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*Processing equipment
