| Proceedings of the Facility Area Network (FAN) Workshop |
OCT 2004 |
108 pages |
| Authors:
Francois Grobler; Jeffrey G. Kirby; E. W. East; ENGINEER RESEARCH AND DEVELOPMENT CENTER CHAMPAIGN IL CONSTRUCTION ENGINEERING RESEARCH LAB
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 | The Facilities Area Network (FAN) Workshop was hosted in February 2004 by the U.S. Army Engineer Research and Development Center (ERDC) as part of Consolidated Facility Object Model (CFOM) project. The purpose of that work is to develop prototype projects in design, construction, and operations that demonstrate the benefits of secure web service confederations. The FAN Work-shop was convened as part of the goal-setting phase of the CFOM project to ... |
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| Test Specification for the Alternate Repair Verification Process of the Finnish Air Force Digital Memory Unit Writer |
30 SEP 2004 |
11 pages |
| Authors:
Michael E. Trenchard; Lancelot Riedlinger; NAVAL RESEARCH LAB STENNIS SPACE CENTER MS MAPPING CHARTING AND GEODESY BRANCH
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| The Digital Memory Unit Writer (DMU) is a ruggedized optical drive assembly built by Honeywell. The DMU writer is used specifically to write specially formatted map data to militarized Aircraft Optical Disks (AOD) for use in the AN/ASQ-l96 Digital Map System (consisting of both a Digital Map Computer and a DMU reader) of both U.S. and ally AV-8B Harrier and F/A-18 Hornet aircraft. The AN/ASQ-196 and its support equipment (including ... |
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| The Second Path: The Role of Algorithms in Maintaining Progress in DSP |
30 SEP 2004 |
10 pages |
| Authors:
Mark A. Richards; GEORGIA INST OF TECH ATLANTA
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| Digital Signal Processing is "...That discipline which has allowed us to replace a circuit previously composed of a capacitor and a resistor with two anti-aliasing filters, an A-to-D and a D-to-A converter, and a general purpose computer (or array processor) so long as the signal we are interested in does not vary too quickly." - Prof. Tom Barnwell, Georgia Tech |
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| Digital IF Standardization |
30 SEP 2004 |
12 pages |
| Authors:
PENTEK INC CORAOPOLIS PA
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| Over the last several years, many large government and industrial customers of communication systems have been requesting the purveyors of RF receiver/transmitter equipment, signal digitization and conversion equipment, and signal processing equipment to standardize on a single interconnect methodology. It is desirable to standardize the format of the digital IF used in these systems so that a marketplace of interoperable products can serve the SIGINT, Aerospace and other communications-oriented communities. ... |
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| OMG Data-Distribution Service (DDS): Architectural Overview |
30 SEP 2004 |
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| Authors:
Gerardo Pardo-Castellote; REAL-TIME INNOVATIONS INC SUNNYVALE CA
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 | The OMG Data-Distribution Service (DDS) is a new specification for publish-subscribe data-distribution systems. The purpose of the specification is to provide a common application-level interface that clearly defines the data- distribution service. The specification describes the service using UML, providing a platform-independent model that can then be mapped into a variety of concrete platforms and programming languages. This paper introduces the OMG DDS specification, describes the main aspects of the ... |
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| Versatile Tiled-Processor Architectures: The Raw Approach |
30 SEP 2004 |
33 pages |
| Authors:
Rodric M. Rabbah; Ian Bratt; Anant Agarwal; Krste Asanovic; MASSACHUSETTS INST OF TECH CAMBRIDGE ARTIFICIAL INTELLIGENCE LAB
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| This presentation will describe the Raw architecture, its implementation, and performance. We will focus on Raw's ability to support a diverse set of applications (ranging from desktop to embedded workloads) and multiple forms of parallelism (including instruction-level parallelism (ILP) for desktop applications, and stream parallelism for embedded computing) as represented by the VersaBench suite. We will also report detailed performance measurements that quantify the versatility of Raw compared to some ... |
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| Dynamo: A Runtime Codesign Environment |
30 SEP 2004 |
7 pages |
| Authors:
Heather Quinn; Miriam Leeser; L. A. Smith-King; NORTHEASTERN UNIV BOSTON MA DEPT OF ELECTRICAL AND COMPUTER ENGINEERING
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| Systems using Field Programmable Gate Array (FPGA) boards have been proven effective for gaining one to three orders of magnitude speed-up over systems based solely on PCs. Signal and image processing applications are especially attractive for implementation on FPGAs as their computationally intensive and massively parallel algorithms can effectively take advantage of the FPGA architecture. In moving part of an algorithm to hardware, one must consider overhead costs as well ... |
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| Broadband Time-Frequency Analysis Using a Multicomputer |
30 SEP 2004 |
23 pages |
| Authors:
John Saunders; MERCURY COMPUTER SYSTEMS INC CHELMSFORDMA
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| Time-frequency analysis techniques are used to produce a plot of a signal's power spectrum as a function of time. The most well-known time- frequency representation is the spectrogram. Although relatively simple to compute, it suffers from having a significant limitation in that it cannot offer good time or frequency resolution simultaneously. To overcome this weakness, many other representations have been developed that provide combined high resolution over time and frequency. ... |
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| SAE AADL: An Industry Standard for Embedded Systems Engineering |
30 SEP 2004 |
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| Authors:
Peter Feiler; CARNEGIE-MELLON UNIV PITTSBURGH PA SOFTWARE ENGINEERING INST
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| SAE AADL and OSATE: ENABLERS OF EMBEDDED SYSTEMS RESEARCH: Industry standard architecture modeling notation & model interchange format facilitates: Interchange of architecture models between contractors & subcontractors; Common architecture model for non-functional system property analysis from different perspectives; In-house prototyping of project specific architecture analysis & generation; Architecture research with access to industrial models; and industry exposure to research results. |
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| The Evaluation of GPU-Based Programming Environments for Knowledge Discovery |
30 SEP 2004 |
20 pages |
| Authors:
John Johnson; Randall Frank; Sheila Vaidya; LAWRENCE LIVERMORE NATIONAL LAB CA
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| Revolutionary advances in computer graphics technologies, driven by the needs of 3D gaming, have resulted in specialized SIMD floating point rendering engines known as GPUs. These GPUs are programmed via graphics libraries such as OpenGL, but have very general programming architectures. These cards are handily exceeding Moore's law performance predictions and are expected to continue to do so for some time. The size and cost competitive nature of the gaming ... |
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| An Efficient Architecture for Ultra Long FFTs in FPGAs and ASICs |
30 SEP 2004 |
18 pages |
| Authors:
Tom Dillon; DILLON ENGINEERING INC EDINA MN
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| This presentation outlines an architecture for efficient Ultra Long FFTs for use in FPGAs and ASICs. Analysis of accuracy, performance, cost and power consumption are presented. FFTs are at the heart of many real time signal processing applications and Ultra Long FFTs are quite often used for frequency analysis and communications applications. As the processing requirements increase, the use of FPGAs and ASICs become the logical choice for implementing real ... |
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| Implementing Modal Software in Data Flow for Heterogeneous Architectures |
30 SEP 2004 |
20 pages |
| Authors:
James Steed; Kerry Barnes; William Lundgren; GEDAE INC MOUNT LAUREL NJ
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| Software for embedded systems is often based on distinct processing modes. A simple example of such modal behavior is a radar system that switches between search mode and tracking mode as targets are located. In complex software systems, the system may have dozens of modes, including sub-modes, forming a deep hierarchy. Such large embedded systems often must be implemented on boards of multiple digital signal processors (DSP). Increasingly, field programmable ... |
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| High Performance Embedded Computing Using Field Programmable Gate Arrays |
30 SEP 2004 |
32 pages |
| Authors:
Charlie Cump; Craig Petrie; Malachy Devlin; Keith Regester; NALLATECH INC LOS ALTOS CA
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| Over the last decade, the performance capabilities of FPGAs have increased exponentially. Leading vendors such as Xilinx and Altera have improved the functionality of their reconfigurable devices through the inclusion of memory, processors, multi-gigabit transceivers, and multipliers to the basic FPGA architecture. The result is a flexible, high performance processing device able to perform low latency, parallel processing tasks with low power consumption. In order to exploit the obvious benefits ... |
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| Virtual Prototyping and Performance Analysis of RapidIO-Based System Architectures for Space-Based Radar |
30 SEP 2004 |
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| Authors:
David Bueno; Chris Conger; Adam Leko; Ian Troxel; Alan D. George; FLORIDA UNIV GAINESVILLE COLL OF ENGINEERING
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| Space-Based Radar (SBR) processing is a processor- and communication- intensive HPEC application that presents unique design challenges. This talk will concentrate on the presentation of simulation results of mapping a parallel Ground Moving Target Indicator (GMTI) application on an embedded multiprocessor satellite processing system featuring a RapidIO interconnection network. We consider three partitionings of a real-time GMTI algorithm executed on systems of different sizes and topologies. Each partitioning's system performance ... |
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| HPEC Related VITA Standards: An Update |
30 SEP 2004 |
24 pages |
| Authors:
Randy Banton; MERCURY COMPUTER SYSTEMS INC CHELMSFORDMA
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| As compared to present day IEEE 1101.x standards.... 1. Board Space & Volume (Space-saving methodologies possible; New allocations of PWB thickness for high-density routing and power distribution; Increased secondary-side components heights) 2. Ruggedization (Improved methodologies for "out of the box" MIL-deployable ruggedization) 3. Thermal Management (Unification of air-, conduction-, liquid-flow-thru-, and spray cooling methods; Improve ability to thermally manage secondary side of PWB; Allow for significant thermal planes in the ... |
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| Adaptive Mapping of Linear DSP Algorithms to Fixed-Point Arithmetic |
30 SEP 2004 |
25 pages |
| Authors:
Lawrence J. Chang; Yevgen Voronenko; Markus Pueschel; Inpyo Hong; CARNEGIE-MELLON UNIV PITTSBURGH PA DEPT OF ELECTRICAL AND COMPUTER ENGINEERING
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| Embedded DSP (digital signal processing) applications are typically implemented using fixed point arithmetic -- in hardware to reduce area requirements and increase throughput, but also in software since most embedded processors do not provide floating point arithmetic. Consequently, the developer is confronted with the difficult task of deciding on the fixed point format, i. e., the number of integer and fractional bits to avoid overflow and ensure sufficient accuracy. For ... |
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| Pulse Compression Made Easy With VSIPL++ |
30 SEP 2004 |
14 pages |
| Authors:
Brian Chase; Wenhao Wu; Dave Leimbach; Rick Pancoast; Anthony Skjellum; VERARI SYSTEMS SOFTWARE INC BIRMINGHAM AL
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| The recent introduction of several template based strategies suggests that C++ may soon become a suitable choice for technical and scientific computing applications. For certain cases, (e.g., matrix multiplications) inline function calls and template code outperforms straight C code. These similar technologies all share a common set of effective strategies that may be summarized as follows: 1) Avoid excessive temporary copies of objects; 2) Make shallow copies instead of deep ... |
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| Amending Moore's Law for Embedded Applications |
29 SEP 2004 |
13 pages |
| Authors:
Richard W. Linderman; AIR FORCE RESEARCH LAB ROME NY INFORMATION DIRECTORATE
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| CONTRIBUTION of Moore's Law to Improvements of Embedded Systems: * Price/Performance: Gigaflops/$M affordability * Memory Capacity: programming simplifications * Steep memory hierarchy: programming inefficiencies and complexities * New flexibilities: e.g., reconfigurable hardware * New complexities: software and parallelism * Dramatic new system capabilities. |
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| Roadmapping the Semiconductor Industry: Are We Reaching the End of the Road? (HPEC 2004 Panel Session: Amending Moore's Law for Embedded Applications) |
29 SEP 2004 |
18 pages |
| Authors:
Bob Schaller; COLLEGE OF SOUTHERN MARYLAND LEONARDTOWN
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| This document contains briefing charts on The Road to Technology Roadmaps, HPEC 2004 Panel Session. |
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| Requirements for Scalable Application Specific Processing in Commercial HPEC |
28 SEP 2004 |
18 pages |
| Authors:
Steven Miller; SILICON GRAPHICS INC MOUNTAIN VIEW CA
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| More and more High Performance Embedded Computing (HPEC) leverages technology from commercial high performance computing systems. To date, HPEC has only tapped the lower end of commercial high performance computing technology. As more of the advanced commercial technology moves into the embedded space, this presents a unique opportunity to change the fundamentals of how HPEC solutions are addressed. Within HPEC, two types of application specific processing elements -- reconfigurable and ... |
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| Software Architecture for Morphing in Polymorphous Computing Architectures |
28 SEP 2004 |
8 pages |
| Authors:
Daniel P. Campbell; Mark A. Richards; Dennis M. Cottel; Randall R. Judd; GEORGIA INST OF TECH ATLANTA
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| To exploit the capabilities of PCA hardware while retaining as much end-user portability and performance as possible, the Morphware Forum (www. morphware.org), an informal consortium of PCA contractors and other selected participants, is creating an application development framework, called the Morphware Stable Interface (MSI). A key capability envisioned for PCA systems is morphing, the reconfiguration and re-allocation of PCA hardware resources within a chip in response to various events. Morphing ... |
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| Timing-Accurate Storage Emulation: Evaluating Hypothetical Storage Components in Real Computer Systems |
13-Sep-2004 |
221 pages |
| Authors:
John L Griffin; CARNEGIE-MELLON UNIV PITTSBURGH PA DEPT OF ELECTRICAL AND COMPUTER ENGINEERING
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| Timing-accurate storage emulation offers a unique capability: flexibility of simulation with the reality of experimental measurements. This allows a researcher to experiment with not-yet-existing storage components in the context of real systems executing real applications. A timing-accurate storage emulator appears to the system to be a real storage component with service times matching a model of the component. This allows simulated components to be plugged into real systems, which can ... |
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| RATS: Reactive Architectures |
SEP 2004 |
61 pages |
| Authors:
Marc Christensen; Fouad Kiamelev; Michael Haney; Charlie Kuznia; Stephen Crago; UNIVERSITY OF SOUTHERN CALIFORNIA MARINA DEL REY INFORMATION SCIENCES INST
|
| This project had two goals: To build an emulation prototype board for a tiled architecture and to demonstrate the utility of a global inter-chip free- space photonic interconnection fabric for polymorphous computer architectures (PCA). The free-space optics part of the project focused on two critical issues to validate the use of ultra-high-capacity global free- space interconnection fabrics for polymorphous computing architectures. These issues fell into the categories of interface issues ... |
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| Information Security and Wireless: Alternate Approaches for Controlling Access to Critical Information |
SEP 2004 |
91 pages |
| Authors:
Winsome Nandram; NAVAL POSTGRADUATE SCHOOL MONTEREY CA
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| The advent of Wireless Local Area Networking (WLAN) has seen a widespread adoption of its technology and functionality in many different areas. Many studies show more and more organizations are extending their networks to incorporate wireless devices and their applications. Permitting wireless devices to access private networks however, further complicates the tasks of protecting the network and its resources from unauthorized access. Now that they have become a significant element ... |
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| Simulating Clouds with Procedural Texturing Techniques Using the GPU |
SEP 2004 |
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| Authors:
Georgios E. Tarantilis; NAVAL POSTGRADUATE SCHOOL MONTEREY CA
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| Many 3D training simulations employ static, and to some extent, simplistic natural phenomena representation that often leaves much to be desired. Taking advantage of the latest advancements in computer graphics hardware allows modeling dynamic natural phenomena such as clouds. Specifically, utilizing procedural techniques and high-level shading languages, it is possible to produce considerably more realistic simulations. This thesis designed and implemented a visual simulation component, which renders convincing clouds using ... |
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| An Architectural Framework for Describing Supervisory Control and Data Acquisition (SCADA) Systems |
SEP 2004 |
122 pages |
| Authors:
Michael P. Ward; NAVAL POSTGRADUATE SCHOOL MONTEREY CA
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| Two recent trends have raised concerns about the security and stability of Supervisory Control and Data Acquisition (SCADA) systems. The first is a move to define standard interfaces and communications protocols in support of cross-vendor compatibility and modularity. The second is a move to connect nodes in a SCADA system to open networks such as the Internet. Recent failures of critical infrastructure SCADA systems highlight these concerns. To ensure continued ... |
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| Particle Simulation of Plume-Plume and Plume-Surface Interactions |
SEP 2004 |
7 pages |
| Authors:
S. F. Gimeishein; A. D. Ketsdever; D. C. Wadsworth; CALIFORNIA UNIV LOS ANGELES DEPT OF MECHANICAL AND AEROSPACE ENGINEERING
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| Numerical modeling of two- and three-dimensional low Reynolds number gas flows from small nozzles has been performed using the direct simulation (DSMC) method. The objective of this effort is to gain an improved understanding of performance and plume interaction phenomena for low thrust devices and thus improve the design and optimization process for a variety of micro-propulsion systems. Simulations were performed for a wide range of flow parameters using the ... |
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| Picosecond-Accuracy Digital-to-Time Converter for Phase-Interpolation DDS |
SEP 2004 |
13 pages |
| Authors:
F. Baronti; D. Lunardini; R. Roncella; R. Saletti; PISA UNIV (ITALY) DIPARTIMENTO DI INGEGNERIA DELL' INFORMAZIONE
|
| A high-resolution CMOS Digital-to-Time Converter for Direct-Digital- Synthesis (DDS) applications is presented in this paper. The novel architecture permits one to perform 4096 phase-interpolation levels introducing a delay proportional to a 12-bit digital control word with a resolution of about 2 ps. The virtual multiplication of the 120 MHz accumulator clock frequency by the factor 4096 is, thus, realized achieving a great reduction of the DDS output spurious components. The ... |
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| A High-Precision Counter Using the DSP Technique |
SEP 2004 |
9 pages |
| Authors:
Shang-Shian Chen; Po-Cheng Chang; Hsin-Min Peng; Chia-Shu Liao; TELECOMMUNICATION LABS TAOYUAN (TAIWAN)
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| A high-precision counter using a digital signal processor (DSP) is designed for phase and frequency measurement. We use an analog-to-digital converter (ADC) to sample the device under test (DUT). Once the signal is digitized, the DSP will be used to run the phase correlation and obtain the necessary information. In our design, the counter is implemented on the Texas Instrument (TI) TMS329C6201 digital signal processor. The sample data from the ... |
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| An Augmented Virtuality Scientific Data Center |
SEP 2004 |
15 pages |
| Authors:
Jerry Clarke; John Vines; Eric Mark; ARMY RESEARCH LAB ABERDEEN PROVING GROUND MD
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| Augmented Virtuality can be effective in the analysis of physics- based computational simulations. By providing context and additional detail not always available in purely virtual systems, the effective addition of physical objects into a virtual scene greatly enhances the intuitive objective of the original calculation. The U.S. Army Research Laboratory has developed an Augmented Virtuality system for the investigation of physics-based simulations. Constructed from commodity components, unique projection screen material, ... |
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| Security and Survivability Reasoning Frameworks and Architectural Design Tactics |
SEP 2004 |
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| Authors:
Robert J. Ellison; Andrew P. Moore; Len Bass; Mark Klein; Felix Bachmann; CARNEGIE-MELLON UNIV PITTSBURGH PA SOFTWARE ENGINEERING INST
|
| The Software Engineering Institute (SEI) has been investigating disciplined software architecture design for several years. The SEI approach includes a collection of "quality attribute reasoning frameworks" that understand both quality attribute reasoning and how architects design for the quality attribute under particular situations. The approach was first applied to the quality attributes of modifiability and performance. This report is an initial attempt to use the same method for the related ... |
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| The Mercury System: Embedding Computation into Disk Drives |
20 AUG 2004 |
38 pages |
| Authors:
Roger D. Chamberlain; Ron K. Cytron; Mark A. Franklin; Ronald S. Indeck; WASHINGTON UNIV ST LOUIS MO
|
| Having inexpensive data storage has enabled the amassing of vast amounts of information. At present, these data sets far exceed the capacity of modern processors, so searching them has become a serious challenge. In a recent invited talk at the High Performance Embedded Computing Workshop, John Reynders of Celera Genomics commented that, "The size of the databases we deal with is no longer measured in terabytes, but in exabytes." The ... |
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| Optimizing System Compute and Bandwidth Density for Deployed HPEC applications |
20 AUG 2004 |
20 pages |
| Authors:
Randy Banton; Richard Jaenicke; MERCURY COMPUTER SYSTEMS INC CHELMSFORDMA
|
| Many high-end deployed military and commercial applications share a common need to achieve high to very high compute and bandwidth density in the smallest possible volume. In addition, deployed military applications layer on additional environmental requirements, such as higher levels of shock, vibration, endurance vibration, temperature, and condensing humidity. Each of these requirements adds constraints on the solution space for maximizing compute and communication density. Not all HPEC applications can ... |
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| Beamforming for Radar Systems on COTS Heterogeneous Computing Platforms |
20 AUG 2004 |
33 pages |
| Authors:
Jeffrey A. Rudin; MERCURY COMPUTER SYSTEMS INC CHELMSFORDMA
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| The introduction of high-speed, analog-to-digital converters has resulted in many of the traditional front-end and sub-array combining functions of multi-function, phased-array radar systems being performed in the digital rather than in the analog domain. Due to the intense amount of processing that is required, many of these functions had to be realized in hardware. This was originally accomplished using VLSI ASICs. However, the advent of multi-million, gate field-programmable gate arrays ... |
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| VSIPL for Diverse Architectures (Pentium 4 to DSPs) |
20 AUG 2004 |
23 pages |
| Authors:
Brian Chase; Wenhao Wu; Anthony Skjellum; MPI SOFTWARE TECHNOLOGY INC STARKVILLE MS
|
| Many companies have described their experiences with using Motorola G4 processors to provide the VSIPL CoreLite standard for military and medical computing, and others have described their efforts with highly optimized Core and Core+ profiles. This poster paper uses the experience of MPI Software Technology's existing Core+ optimized VSIPL implementation for G4 as the springboard for supporting other platforms of emerging interest to COTS, defense, medical, and imaging customers. Three ... |
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| The Decomposition of HPEC Applications Mapped to the Natural Decomposition of a Solution Architectures -- Another Way to Think about Solving HPEC Problems |
20 AUG 2004 |
14 pages |
| Authors:
Joe Germann; SKY COMPUTERS INC PEABODY MA
|
| In the past, all large-scale computer architectures that were designed by so-called Digital Signal Processing (DSP) vendors were of the "kitchen sink" approach. Each board unit incorporated all of the features that one could possibly want into a single unified design. Processors, I/O, memory, and interconnects were all available in one product, thereby increasing per slot functionality, but often at the burden of complexity, reliability, and overall cost. While this ... |
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| Health Maintenance System: An Application of Recovery Oriented Computing for HPEC Systems |
20 AUG 2004 |
12 pages |
| Authors:
Gerry Pocock; SKY COMPUTERS INC PEABODY MA
|
| Until recently, the single aspect of HPEC systems that has been most critical has been "performance," in terms of processor speeds and I/O throughput. As processor speeds and I/O throughput have continued to increase, and as the capability to build larger and larger systems has improved, the need for raw performance is becoming less critical. Now, it is the ability to achieve a high level of application availability that is ... |
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| A Parallel Data Mining Toolbox Using MatlabMPI |
20 AUG 2004 |
44 pages |
| Authors:
Parna Khot; Ashok K. Krishnamurthy; Stanley C. Ahalt; John W. Nehrbass; Juan C. Chaves; OHIO STATE UNIV COLUMBUS DEPT OF ELECTRICAL ENGINEERING
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| The ready availability of vast quantities of data has driven the need for data mining algorithms that can discover patterns, correlations and changes in the data. The amount and high dimensionality of the data make data mining an important application for high performance computing Joshi, 2002. The mathematical and interactive nature of many of the data mining algorithm, makes it natural to use a language like MATLAB both to design ... |
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| Considerations for Algorithm Selection and C Programming Style for the SRC-6E Reconfigurable Computer |
20 AUG 2004 |
21 pages |
| Authors:
Russ Duren; Douglas Fouts; NAVAL POSTGRADUATE SCHOOL MONTEREY CA DEPT OF ELECTRICAL AND COMPUTER ENGINEERING
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| The architecture and programming environment of the SRC-6E reconfigurable Computer was presented in the 2002 MAPLD International Conference 1. That paper described how the programmer could trade off chip area for execution speed. In this paper we discuss additional aspects of programming the SRC-6E. In particular we examine classes of algorithms that best benefit from the SRC-6E's architecture. Additionally, we examine how the SRC-6E compiler interprets various C language constructs. ... |
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| VSIPL++/FPGA Design Methodology |
20 AUG 2004 |
38 pages |
| Authors:
Jules Bergmann; Susan Emeny; Peter Bronowicz; AIR FORCE RESEARCH LAB ROME NY INFORMATION DIRECTORATE
|
| This paper describes a hardware/software codesign methodology for hybrid hardware and software systems. The methodology integrates VSIPL++ for software design and a portable, composable hardware design method based on streams. The hardware design is portable and scalable from design/test systems to the target system and to future technologies. The methodology increases productivity by providing a concise function description in both hardware and software and by providing a streamlined interface between ... |
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| High-Performance Scalable Base-4 Fast Fourier Transform Mapping |
20 AUG 2004 |
29 pages |
| Authors:
J. G. Nash; CENTAR LOS ANGELES CA
|
| This paper describes a novel, scalable, parallel Fast Fourier Transform (FFT) architecture mapping that supports transform lengths that are not powers of two or four, that provides low latency as well as high throughput, that can do both 1-D and 2-D Discreet Fourier Transforms (DFTs), that is ideally suited to today's complex FPGA architectures, that possesses all the regularity and design simplicity of systolic arrays, and that is naturally suited ... |
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| High-Performance Linear Algebra Processor using FPGA |
20 AUG 2004 |
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| Authors:
J. R. Johnson; P. Nagvajara; C. Nwankpa; DREXEL UNIV PHILADELPHIA PA DEPT OF ELECTRICAL AND COMPUTER ENGINEERING
|
| With recent advances in FPGA (Field Programmable Gate Array) technology it is now feasible to use these devices to build special purpose processors for floating point intensive applications that arise in scientific computing. FPGA provides programmable hardware that can be used to design custom hardware without the high-cost of traditional hardware design. In this talk we discuss two multi-processor designs using FPGA for basic linear algebra computations such as matrix ... |
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| Sensing-Computing-Actuating Multi Target Tracking System |
12 AUG 2004 |
14 pages |
| Authors:
Csaba Rekeczky; ANALOGIC COMPUTERS LTD BUDAPEST (HUNGARY)
|
| This report results from a contract tasking AnaLogic Computers Ltd. as follows: The Grantee will investigate a real-time multi-target tracking and actuating system. The tracking algorithm will be implemented on the Cellular Neural Network (CNN) visual microprocessor technology (called the ACE-BOX Visual Computer with the ACE16K CNN chip). Tracking will include selective identification based on shape and size. A high-speed CMOS camera will provide image streams of moving objects displayed ... |
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| The V1.0 'Pushpin' Nixel 2-D Self-Assembling Display Array |
AUG 2004 |
24 pages |
| Authors:
Joseph Jacobson; Neil Gershenfeld; Bill Butera; MASSACHUSETTS INST OF TECH CAMBRIDGE MEDIA LAB
|
| This report details the results of the MIT - RF Nixel Program. The RF Nixel Program represents a novel architecture for display systems based on an ensemble of Nixel display elements. Each Nixel element comprises a display element (pixel), lightweight computation sufficient to run self -assembling software code elements and local communications. A proof-of-principle hardware implementation (The Vi .0 Pushpin' Nixel 2D array) was carried out and used to successfully ... |
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| Pool Data Acquisition System Documentation |
AUG 2004 |
35 pages |
| Authors:
Scott B. Robinson; Laurie A. Blanchard; Robert Soares; ARMY RESEARCH INST OF ENVIRONMENTAL MEDICINE NATICK MA THERMAL AND MOUNTAIN MEDICINE DIVISION
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| This report describes a data acquisition system developed to obtain body temperature measurements for human volunteers during cold exposure. Since acceptable commercial systems are not available, this system was custom-built to acquire data using National Instruments hardware components and LabVIEW 6.0 Development Software. The system works by integrating signals collected by hardware devices, and the software processes/manipulates by using Virtual Instruments (VI's). This report provides detailed documentation for the construction ... |
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| An Evaluation of Stereoscopic Digital Mammography for Earlier Detection of Breast Cancer and Reduced Rate of Recall |
AUG 2004 |
59 pages |
| Authors:
David J. Getty; BBN TECHNOLOGIES CAMBRIDGE MA
|
| The goal of this project is to evaluate stereoscopic digital mammography, compared to standard, non-stereo digital mammography, for the earlier detection of breast cancer and reduced rate of patient recall for further workup. During the project, approximately 2000 women at elevated risk for development of breast cancer will receive both standard (non- stereo) and stereo digital mammograms at the Emory Breast Clinic. In this second year of the project, we ... |
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| Exploiting the Cognitive and Social Benefits of Physically Large Displays |
AUG 2004 |
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| Authors:
Desney S. Tan; CARNEGIE-MELLON UNIV PITTSBURGH PA DEPT OF COMPUTER SCIENCE
|
| There exists an emerging trend in the workplace towards multiple display systems. Within these workplaces, large wall-sized displays are becoming prevalent. Although researchers have articulated qualitative benefits of large displays, little has been done to systematically quantify and exploit these benefits. My work is composed of three distinct components, each contributing to an improved understanding of physically large displays. First, I isolate and study specific cognitive benefits unique to large ... |
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| Satellite Radiance Data Assimilation: Code Migration to Scalable Architectures |
09 JUL 2004 |
42 pages |
| Authors:
George Modica; Thomas Nerkhorn; ATMOSPHERIC AND ENVIRONMENTAL RESEARCH INC LEXINGTON MA
|
| We developed a highly scalable version of the MM5 4d-Var application. The application consists of a meteorological analysis code that provides accurate depictions of the state of the atmosphere, has been applied successfully to a large number of cases, and the results have been documented in peer reviewed forums. Prior to this project, this code was optimized for vector computer architectures. By rewriting this code in order to make it ... |
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| Digital Proficiency Levels for the Brigade and Battalion Battle Staff |
JUL 2004 |
78 pages |
| Authors:
Bruce C. Leibrecht; Karen J. Lockaby; Andrew M. Perrault; Larry L. Meliza; NORTHROP GRUMMAN MISSION SYSTEMS RESTONVA
|
| This report results from ongoing work to develop a digital proficiency measurement architecture that includes the battle staff equipped with the Army Tactical Command and Control System (ATCCS). The report first examines primary dimensions of ATCCS-enabled performance, including major system capabilities, high- payoff user skills and tasks, and network management skills. It then explores how ATCCS exploitation contributes to critical staff functions, with an emphasis on integration across Battlefield Operating ... |
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| Optimization of Keyboard Design for Specialized Text Entry |
JUL 2004 |
7 pages |
| Authors:
Gregory Francis; Clarence E. Rash; PURDUE UNIV LAFAYETTE IN
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| As computers are introduced into ever more devices with new methods of inputting information, there has been interest in how to optimally design the information input system. We build on previous work along these lines to demonstrate a program that can quickly build the optimal keyboard layout that minimizes the time required to input a given set of data. This approach makes it possible to create different keyboard designs for ... |
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Computer Hardware
