| The Binary Phase Only Filter as an Image Watermark |
12 JAN 2004 |
5 pages |
| Authors:
Farid Ahmed; Ira S. Moskowitz; CATHOLIC UNIV OF AMERICA WASHINGTON DC DEPT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE
|
 | We describe our new method for watermarking digital images. Our work is motivated by the study of phase only filters in Fourier optics. In this paper we concentrate on grey scale images, even though our method works for color also. We take the discrete Fourier transform of an image and determine a signature based upon a binary phase-only filter (BPOF). We replace certain frequency magnitudes with this BPOF. This serves ... |
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| Power Electronics Building Blocks, "Plug and Play", Hardware and Software Control Architectures |
08 JAN 2004 |
233 pages |
| Authors:
Dushyan Boroyevich; VIRGINIA POLYTECHNIC INST AND STATE UNIV BLACKSBURG OFFICE OF SPONSORED PROGRAMS
|
| The main objective of this project has been to investigate means to standardize communications and control systems in order to develop seamless "Plug and Play" (PnP) power electronics. The intent within has been to pave the way for the development of reconfigurable low-cost, high reliability, and easy to use power processing devices. Such devices, known as Power Electronics Building Blocks (PEBBs), would certainly encourage the proliferation of power electronics into ... |
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| Diamond-Shaped Semiconductor Ring Lasers for Analog to Digital Photonic Converters |
JAN 2004 |
19 pages |
| Authors:
Malcolm Green; AIR FORCE RESEARCH LAB ROME NY SENSORSDIRECTORATE
|
| Photonic/ optoelectronic analog to digital converters (ADCs) have advantages in areas such as precise sampling times, narrow sampling apertures, and the ability to sample without contaminating the incident signal. They also have potential to offer the highest sampling rates and bandwidths. Significant challenges remain in the development of photonic ADC architectures and associated components (e.g. compactness, reduce power consumption v. efficiency, improved mechanical and thermal stability, etc.). Monolithically integrated photonic ... |
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| Optically Programmable Field Programmable Gate Arrays (FPGA) Systems |
JAN 2004 |
118 pages |
| Authors:
Jose Mumbru; George Panotopoulos; Demetri Psaltis; CALIFORNIA INST OF TECH PASADENA DEPT OF ELECTRICAL ENGINEERING
|
| This report presents the results of research in the use of holographic modules in optoelectronic systems, their applications, and the characterization of polymer materials on which to record volume holograms for these modules. The first chapter makes the case that a direct interface between an optical memory and a chip integrating detectors and logic circuitry can better utilize the high parallelism inherent in holographic modules. Introduced also is the idea ... |
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| M3T: Morphable Multithreaded Memory Tiles |
JAN 2004 |
41 pages |
| Authors:
Josep Torrellas; Ben Abbott; Ted Bapty; Bob Bassett; Hubertus Franke; ILLINOIS UNIV AT URBANA
|
| The Morphable Multithreaded Memory Tiles (M3T) system proves that a polymorphous computing system polymorphous hardware and a complete polymorphous software environment is orders of magnitude more cost effective than conventional computing systems. The cornerstone of M3T is two main contributions: (1) architectural support that enables the processor cores and memories in an M3T chip to reconfigure at run time, allowing the processing architecture to morph or reconfigure itself into different ... |
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| Power Analyzer for Pocket Computing (PAPC) |
JAN 2004 |
58 pages |
| Authors:
Trevor Mudge; Nam S. Kim; Jeffrey Ringenberg; Taeho Kgil; MICHIGAN UNIV ANN ARBOR DEPT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE
|
| Under this contract researchers at the Universities of Michigan and Colorado have developed an innovative and practical power evaluation tool, Power Analyzer, suitable for calculating power consumption for complete computer systems. Power Analyzer will be initially targeted to pocket computers where computing and communication place strong demands on the portable power supply. |
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| Digital Skills Training for Net-Centric Operations |
JAN 2004 |
35 pages |
| Authors:
Brooke B. Schaab; J. D. Dressel; Franklin L. Moses; ARMY RESEARCH INST FOR THE BEHAVIORAL AND SOCIAL SCIENCES ALEXANDRIA VA
|
| Multiple research activities identified training methods that enhance Army net-centric operations where Soldiers use sophisticated digital systems that interact over an electronic network. Researchers collected information from Soldiers over five years, from 1999 to 2003, to understand how "going digital" changes responsibilities and training needs. Soldiers documented training preferences and shared frustrations and successes as their understanding and expertise evolved over time. This special report presents principles and recommendations, including ... |
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| Implicit Memory, Perception and the Rapid Deployment of Visual Attention and Action |
2004 |
6 pages |
| Authors:
Ken Nakayama; PRESIDENT AND FELLOWS OF HARVARD COLL CAMBRIDGE MA OFFICE OF SPONSORED RESEARCH
|
| The learning of the deployment of transient attention is an entirely new yet robust phenomenon. We found that it is mediated by a unique primitive short term memory system which learns features, not objects. Yet it is object centered and not retinotopic. This learning is graded, incremental and short lived. We also investigated longer term perceptual learning: very short naps during the afternoon can enhance perceptual learning dramatically, that in ... |
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| Advanced High and Low Fidelity HPC Simulations of FCS Concept Designs for Dynamic Systems |
2004 |
9 pages |
| Authors:
S. S. Sandhu; R. Kanapady; K. K. Tamma; MINNESOTA UNIV MINNEAPOLIS DEPT OF MECHANICAL ENGINEERING
|
| The Objective Force concept of the future US Army is to fight wars with adversaries, which are fast evolving and have adaptive capabilities. To have advantage over these adversaries, new weapon system designs and development should be modular to operate as system-of systems and should have short development cycles. This requires validated high performance computational models within this modular framework and the need to effectively utilize the High Performance Computing ... |
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| Representational and Inferential Requirements for Diagrammatic Reasoning in the Entity Re-Identification Task |
2004 |
3 pages |
| Authors:
B. Chandrasekaran; U. Kurup; B. Banerjee; OHIO STATE UNIV COLUMBUS DEPT OF COMPUTER SCIENCE AND ENGINEERING
|
| Diagrammatic reasoning is ubiquitous in Army reasoning: situation understanding and planning in the Army both involve representing aspects of the situation and plans in the form of diagrams. We have been developing a general architecture to support diagrammatic reasoning for Army applications, and in an earlier report 1 we discussed an application in simple maneuver recognition. Our research strategy has been to investigate a variety of applications, each bringing additional ... |
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| A Doctoral Program With Specialization in Information Security |
2004 |
9 pages |
| Authors:
Cynthia E. Irvine; Timothy E. Levin; NAVAL POSTGRADUATE SCHOOL MONTEREY CA
|
| Abstract: A doctoral program in computer science with a specialization in information security is described. The focus of the program is constructive security. Key elements of the program are the strong computer science core upon which it builds, coursework on the theory and principles of information assurance, and a unifying research project. The doctoral candidate is a member of the project team, whose research contributes to the goals of the ... |
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| Communication-Driven Codesign for Multiprocessor Systems |
2004 |
246 pages |
| Authors:
Neal K. Bambha; MARYLAND UNIV COLLEGE PARK DEPT OF ELECTRICAL AND COMPUTER ENGINEERING
|
| Several trends in technology have important implications for embedded systems of the future. One trend is the increasing density and number of transistors that can be placed on a chip. This allows designers to fit more functionality into smaller devices, and to place multiple processing cores on a single chip. Another trend is the increasing emphasis on low power designs. A third trend is the appearance of bottlenecks in embedded ... |
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| Dataflow Interchange Format and a Framework for Processing Dataflow Graphs |
2004 |
130 pages |
| Authors:
Fuat Keceli; MARYLAND UNIV COLLEGE PARK DEPT OF ELECTRICAL AND COMPUTER ENGINEERING
|
| Digital Signal Processing (DSP) applications are often designed with tools based on dataflow graphs and the increasing number of such tools shows the need for a common intermediate graph representation for exchanging dataflow information. In this work, we present the dataflow interchange format (DIF), a platform-independent textual language that is geared towards capturing the semantics of graphical design tools for DSP system design. A key objective of DIF is to ... |
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| Energy-Efficient, Utility Accrual Scheduling under Resource Constraints for Mobile Embedded Systems |
2004 |
21 pages |
| Authors:
Haisang Wu; Binoy Ravindran; E. D. Jensen; Peng Li; VIRGINIA POLYTECHNIC INST AND STATE UNIV BLACKSBURG DEPT OF ELECTRICAL AND COMPUTER ENGINEERING
|
| We present an energy-efficient, utility accrual, real-time scheduling algorithm called the Resource-constrained Energy-Efficient Utility Accrual Algorithm (or ReUA). ReUA considers an application model where activities are subject to time/utility function (TUF) time constraints, resource dependencies including mutual exclusion constraints, and statistical performance requirements including activity (timeliness) utility bounds that are probabilistically satisfied. Further, ReUA targets mobile embedded systems where system-level energy consumption is also a major concern. For such a ... |
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| Navigation Function Based Visual Servo Control |
2004 |
18 pages |
| Authors:
J. Chen; D. M. Dason; W. E. Dixon; V. K. Chitrakaran; CLEMSON UNIV SC DEPT OF ELECTRICAL AND COMPUTER ENGINEERING
|
| In this paper, a unique camera mapping between the desired camera feature vector and the desired camera pose (i.e., the position and orientation) is investigated to develop a measurable image Jacobian-like matrix. An image-space path planner is then proposed to generate a desired image trajectory based on this measurable image Jacobian-like matrix and an image space navigation function (NF) (i.e., a special potential field function) while satisfying rigid body constraints. ... |
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| Non-Linear Radio-Frequency Research and Educational Laboratory |
28 DEC 2003 |
15 pages |
| Authors:
Patrick Roblin; OHIO STATE UNIV COLUMBUS DEPT OF ELECTRICAL ENGINEERING
|
| The AFOSR Durip grant was awarded to OSU in May 2003. The OSU research Foundation account RF744774 was subsequently created. The target of this AFOSR Dtirip grant was to acquire a Large Signal Network Analyzer (LSNA). A brief description of the activities which took place in the calendar year 2003 following the award are described below the Summer 2003 establishing the specifications of the LSNA as required by the OSU ... |
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| Digital Antenna Architectures Using Commercial Off the Shelf Hardware |
DEC 2003 |
96 pages |
| Authors:
Cher Shin Eng; NAVAL POSTGRADUATE SCHOOL MONTEREY CA
|
| The changes in war fighting tactics and advancement of technology shape the ways to implement and design multifunction phased array radars. This thesis investigated whether the commercial modulation boards used in the 3-D 2, 4-GHz phased array transmit antenna is capable of wideband performance. The phase of the transmitted signal out of the modulator board was adjusted to provide a phase shift from 0 to 2pi, and the insertion phases ... |
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| Benchmarking and Analysis of the SRC-6E Reconfigurable Computing System |
DEC 2003 |
149 pages |
| Authors:
Kendrick R. Macklin; NAVAL POSTGRADUATE SCHOOL MONTEREY CA
|
| This thesis evaluates the usefulness of the SRC-6E re- configurable computing system for a radar signal processing application and documents the process of creating and importing VHDL code to configure the user definable logic on the SRC-6E. A false-target radar-imaging algorithm was chosen and implemented on the SRC-6E. Data from alternative computational approaches to the same problem are compared to determine the effectiveness of SRC-6E solution. The results show that ... |
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| Testing and Evaluation of the Configurable Fault Tolerant Processor (CFTP) for Space-Based Applications |
DEC 2003 |
269 pages |
| Authors:
Charles A. Hulme; NAVAL POSTGRADUATE SCHOOL MONTEREY CA
|
| With the complexity of digital systems, reliability considerations are important. In many digital systems it is desirable to continuously monitor, exercise, and test the system to determine whether it is performing as desired. Such monitoring may enable automatic detection of failures via periodic testing or through the use of codes and checking circuits (e.g., built-in self-testing). While any complex system requires testing to ensure satisfactory performance, satellite systems require extensive ... |
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| Digital Enhancement of Night Vision and Thermal Images |
DEC 2003 |
|
| Authors:
Chek K. Teo; NAVAL POSTGRADUATE SCHOOL MONTEREY CA
|
 | Low image contrast limits the amount of information conveyed to the user With the proliferation of digital imagery and computer interface between man-and-machine, it is now viable to consider digitally enhancing the image before presenting it to the user, thus increasing the information throughput. This thesis explores the effect of the Contrast Limited Adaptive Histogram Equalization (CLAHE) process on night vision and thermal images With better contrast, target detection and ... |
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| Integrating the Architecture Tradeoff Analysis Method (ATAM) with the Cost Benefit Analysis Method (CBAM) |
DEC 2003 |
|
| Authors:
Robert L. Nord; Mario R. Barbacci; Paul Clements; Rick Kazman; Mark Klein; CARNEGIE-MELLON UNIV PITTSBURGH PA SOFTWARE ENGINEERING INST
|
| The Architecture Tradeoff Analysis Initiative at the Carnegie Mellon Software Engineering Institute (SEl) has developed a number of architecture- centric methods currently in use including the SEISM Architecture Tradeoff Analysis Method (ATAM), the SEl Quality Attribute Workshop (QAW), the SEl Cost Benefit Analysis Method (CBAM), SEl Active Reviews for Intermediate Designs (ARID), and the SE Attribute-Driven Design (ADD) method. Building on our success in developing and piloting a collection of ... |
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| Battlefield Online with Superconductive Systems Technology Demonstration |
DEC 2003 |
68 pages |
| Authors:
J. X. Przybyz; D. L. Miller; Chris Lavoie; Aaron Pesetski; NORTHROP GRUMMAN CORP BALTIMORE MD CRYSTAL SCIENCE AND TECHNOLOGY
|
| The contract for Battlefield Online with Superconductive Systems build upon the success of previous AFRL contracts to develop components based on superconductive electronics for spread spectrum modems. The prior work had demonstrated a low power chip that operated at 2 GHz and performed spread spectrum functions. This contract developed a Digital Correlator and a rapid Synchronizer and demonstrated that the correlation and synchronization could be performed with superconductive digital electronics. ... |
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| Spatial Computation |
DEC 2003 |
225 pages |
| Authors:
Mihai Budiu; CARNEGIE-MELLON UNIV PITTSBURGH PA SCHOOL OF COMPUTER SCIENCE
|
| This thesis presents a compilation framework for translating ANSI C programs into hardware dataflow machines. The framework is embodied in the CASH compiler, a Compiler for Application-Specific Hardware. This style of computation is dubbed Spatial Computation. The first part of this document describes Pegasus, the internal representation of CASH. The most notable of these are a new optimal register-promotion algorithm and partial redundancy elimination for memory accesses based on predicate ... |
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| A Protocol Family for Versatile Survivable Storage Infrastructures |
Dec-2003 |
28 pages |
| Authors:
Gregory R Ganger; Garth R Goodson; Jay J Wylie; Michael K Reiter; CARNEGIE-MELLON UNIV PITTSBURGH PA SCHOOL OF COMPUTER SCIENCE
|
| Survivable storage systems mask faults. A protocol family shifts the decision of which types of faults from implementation time to data-item creation time. If desired, each data-item can be protected from different types and numbers of faults. This paper describes and evaluates a family of storage access protocols that exploit data versioning to efficiently provide consistency for erasure-coded data. This protocol family supports a wide range of fault models with ... |
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| Nanostructured Magnetism for Super-Dense Memories |
30 NOV 2003 |
8 pages |
| Authors:
Ivan K. Schuller; CALIFORNIA UNIV SAN DIEGO LA JOLLA INST FOR PURE AND APPLIED PHYSICAL SCIENCES
|
| In the initial phases, we showed that we can prepare self-supporting masks and that the concept of magnetic stabilization using exchange bias is feasible. We developed instrumentation for the preparation of porous alumina masks on a substrate and automated analysis methods for characterization of dot distribution. During the next phase, we started preparation and characterization of samples grown on Si substrates. Studies of the magnetic properties were started during the ... |
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| THETO - A Fast and High-Quality Partitioning Driven Global Placer |
25 NOV 2003 |
8 pages |
| Authors:
Navaratnasothie Selvakkumaran; George Karypis; MINNESOTA UNIV MINNEAPOLIS DEPT OF COMPUTER SCIENCE
|
| Partitioning driven placement approaches are often preferred for fast and scalable solutions to large placement problems. However, due to the inaccuracy of representing wirelength objective by cut objective the quality of such placements often trails the quality of placements produced by pure wirelength driven placements. In this paper we present THETO, a new partitioning driven global placement algorithm that retains the speed associated with traditional partitioning driven placement algorithms but ... |
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| Nuclear Magnetic Resonance Spectrometer Console Upgrade for a Type II quantum Computer |
19 NOV 2003 |
|
| Authors:
David G. Cory; MASSACHUSETTS INST OF TECH CAMBRIDGE
|
| As proposed, we upgraded the system console on an existing Bruker Instruments, 14 T nuclear magnetic resonance (NMR) spectrometer to enable an improved implementation of type II quantum computers (TTQC). This upgrade is fully functional and has permitted our NMR studies to be moved to higher strength magnetic fields for better sensitivity and spectral dispersion. The TTQC experiments continue in collaboration with Dr. J. Yepez of the Air Force Research ... |
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| A 10-Bit 10 GSPS Optical ADC for Radar Signal Processing |
NOV 2003 |
18 pages |
| Authors:
Eric Donkor; CONNECTICUT UNIV STORRS OFFICE FOR SPONSORED PROGRAMS
|
| Next generation radar systems for tactical aircraft will need to improve aircraft survivability, allow for cooperative multistatic mode of operation, provide efficient anti-jamming features, and compensate for motion- induced clutter. Faster digital processors are required, in particular analog- to-digital converters (ADCs) for digital processing of X-band radar systems. This effort investigated and demonstrated an optoelectronic scheme for a high- speed optical ADC. The system was designed with the following objectives ... |
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| Universal Network Access System |
NOV 2003 |
156 pages |
| Authors:
Kirk Boyer; Bob Davies; TEKTRONIX FEDERAL SYSTEMS INC BEAVERTONOR
|
| Develop and demonstrate a Universal Network Access engine using an innovative bit-rate adaptive demultiplexer/multiplexer, a reconfigurable physical layer protocol engine, and a reconfigurable cell/packet engine. FUNCTION: This work supports Air Force C3I Communications Networks. OPPORTUNITY: The effort will provide the network equivalent of a power adapter/extension cord for flexibility interconnecting a wide range of broadband information sources and local networks over the next generation internet. CONTRIBUTION: The capability to rapidly ... |
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| Architecture Reconstruction Guidelines Third Edition |
NOV 2003 |
|
| Authors:
Rick Kazman; Liam O'Brien; Chris Verhoef; CARNEGIE-MELLON UNIV PITTSBURGH PA SOFTWARE ENGINEERING INST
|
| Architecture reconstruction is the process of obtaining the "as- built" architecture of an implemented system from the existing legacy system. For this process, tools are used to extract information about the system that will assist in building successive levels of abstraction. Although generating a useful representation is not always possible, a successful reconstruction results in an architectural representation that aids in reasoning about the system. This recovered representation is most ... |
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| Architecture Reconstruction of J2EE Applications: Generating Views from the Module Viewtype |
NOV 2003 |
|
| Authors:
Liam O'Brien; Vorachat Tamarree; CARNEGIE-MELLON UNIV PITTSBURGH PA SOFTWARE ENGINEERING INST
|
| This report outlines the application of architecture reconstruction techniques to the Sun Microsystems' Duke's Bank system-a Java2 Platform, Enterprise Edition/Enterprise JavaBeans (J2EE/EJB) application implemented mainly in Java. The goal of the reconstruction was to apply architecture reconstruction techniques to a system implemented in Java to produce a set of views that depict that system's architecture. Decomposition style views of the module view type were used. They focus on the "is ... |
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| Non-Hierarchical Approach to Couple CCIS with M&S |
NOV 2003 |
21 pages |
| Authors:
H. P. Menzler; M. Sieber; MODELING AND SIMULATION INFORMATION ANALYSIS CENTER ALEXANDRIA VA
|
| The use of the term interoperability in certain areas of information technology is also predominant in the military community when talking about multinational Command and Control Information system Environments (CCIS) and Modeling and Simulation (M&S). The Multilateral Interoperability Program (MIP) on the one hand and the Simulation Interoperability Standards Organization (SISO) on the other hand prevail among others. Either community typically has different meaning of the term interoperability and they ... |
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| Teaching Teamwork Online |
Nov 2003 |
5 pages |
| Authors:
Lisa Neal; Eileen Entin; Fuji Lai; APTIMA INC WOBURN MA
|
| We report on the development of an innovative program aimed at providing online teamwork training for distributed professionals performing complex, highly interdependent tasks. Examples of teams for which this training would be appropriate include special purpose (e.g., crisis response) teams within command control organizations and operations centers, special operations teams, and medical teams. To maximize learning and flexibility, the program couples synchronous and asynchronous approaches to online learning, uses video ... |
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| A Philosophical and Technical Comparison of Legion and Globus |
15 OCT 2003 |
23 pages |
| Authors:
Andrew S. Grimshaw; Marty A. Humphrey; Anand Natrajan; VIRGINIA UNIV CHARLOTTESVILLE DEPT OF COMPUTER SCIENCE
|
| Grids are collections of interconnected resources harnessed to satisfy various needs of users. Legion and Globus are pioneering grid technologies. Several of the aims and goals of both projects are similar, yet their underlying architectures and philosophies differ substantially. The scope of both projects is the creation of worldwide grids; in that respect, they subsume several distributed systems technologies. However, Legion has been designed as a virtual operating system (OS) ... |
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| Spike-Based Hybrid Computers |
02 OCT 2003 |
6 pages |
| Authors:
Rahul Sarpeshkar; MASSACHUSETTS INST OF TECH CAMBRIDGE RESEARCH LAB OF ELECTRONICS
|
| This report documents progress made during the period July 1st 2002 to Jan 2003 for the ONR grant 'Spike-Based Hybrid Computers'. It is the fourth and final progress report for this grant. Our progress this year was in three areas: (1) Ultra-Low-Power Time-Based Analog-to-Digital Conversion inspired by neuronal signal representations; (2) An analog integrated circuit memory element for use in learning and adaptive systems, and (3) A predictive comparator with ... |
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| Adaptive Structure Aware Memory Systems |
OCT 2003 |
43 pages |
| Authors:
John B. Carter; UTAH UNIV SALT LAKE CITY
|
| This report describes the design of the Impulse architecture and shows how an Impulse memory system can be used in a variety of ways to improve the performance of data-intensive applications. The Impulse design does not require any modification to processor, cache, or bus designs - all novel hardware functionality resides at the memory controller. As a result, Impulse optimizations can be adopted in conventional systems without major system changes. ... |
|
| High-Temperature, 400 W, DC-to-AC Inverter Using Silicon Carbide Gate Turn- Off Thyristors and p-i-n Diodes |
OCT 2003 |
30 pages |
| Authors:
C. W. Tipton; Stephen B. Bayne; Charles J. Scozzie; Timothy Griffin; Bruce Geil; ARMY RESEARCH LAB ADELPHI MD
|
| A high-temperature, 400 W, DC-to-AC inverter has been developed using silicon carbide gate turn-off thyristors and p-i-n diodes. We demonstrate the inverter driving a three-phase, inductive motor up to 580 W and device case temperatures up to 150 deg C. The inverter circuit was constructed to perform the first characterization of these SiC devices under significant electrical and thermal stresses, investigate the parametric operating space of the SiC devices, and ... |
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| Area, and Power Performance Analysis of a Floating-Point Based Application on FPGAs |
24 SEP 2003 |
35 pages |
| Authors:
Gokul Govindu; Ling Zhuo; Seonil Choi; Padma Gundala; Viktor K. Prasanna; UNIVERSITY OF SOUTHERN CALIFORNIA LOS ANGELES DEPT OF ELECTRICAL ENGINEERING
|
| Almost all signal processing algorithms are initially represented as double precision floating-point in languages such as Matlab. For hardware implementations, these algorithms have to be converted to large precision fixed- point to have a sufficiently large dynamic range. However the inevitable quantization effects and the complexity of converting the floating-point algorithm into a fixed point one, limit the use of fixed-point arithmetic for high precision embedded computing. FPGAs have become ... |
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| Digital Signal Processing at 1GHz in a Field-Programmable Object Array |
24 SEP 2003 |
34 pages |
| Authors:
Dirk R. Helgemo; MATHSTAR INC MINNEAPOLIS MN
|
| Autonomous MAC and ALU processors and register files (three types of Silicon Objects) are implemented with custom logic to achieve 1GHz fixed-point multiply and accumulate. Synchronous programmable interconnect and embedded storage reduces the need for difficult index calculation and the use of external memory for intermediate values. The flexibility of the objects and their interconnect allows the level of parallelism to be chosen freely based on performance requirements and resource ... |
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| Sensor Management and Multisensor Fusion Algorithms for Tracking Applications |
23 SEP 2003 |
5 pages |
| Authors:
Lucy Y. Pao; OFFICE OF NAVAL RESEARCH ARLINGTON VA
|
| The objective of the research under this Office of Naval Research award is to develop multisensor management and fusion algorithms for tracking applications. Under this award the author has achieved a number of results: (1) developed a decorrelated sequence method for distributed fusion that is amenable to general distributed architectures; (2) compared a number of recently proposed multisensor, multitarget tracking algorithms to better understand which algorithms perform better in certain ... |
|
| Efficient Split Radix FFTs in FPGAs |
23 SEP 2003 |
13 pages |
| Authors:
Tom Dillon; DILLON ENGINEERING INC EDINA MN
|
| This presentation outlines methods for split radix FFTs implemented in FPGAs. Analysis of various algorithms with regards to performance, cost and power consumption are presented. FPGAs are rapidly finding their way into high performance DSP applications, specifically real time signal processing applications. Large FPGAs offer a significant cost, size, and power advantage over other alternatives for many front end real time processing operations. FPGAs offer the advantage of short and ... |
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| The eXtreme Adaptive DSP Solution to Sensor Data Processing |
23 SEP 2003 |
14 pages |
| Authors:
Martin Vorbach; Leo Mirkin; SKY COMPUTERS INC PEABODY MA
|
| The new ISR mobile autonomous sensor platforms present a difficult challenge to the current generation of high-speed DSP solutions. The high- bandwidth data streams must be processed with minimal power and heat dissipation. The programmatic needs on the new SR platforms include a rapid pace of technology upgrades, a quick development cycle, and lower costs; especially reduction in the software development costs and risks. These goals conflict with high- cost ... |
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| An Ultra-High Performance Architecture for Embedded Defense Signal and Image Processing Applications |
23 SEP 2003 |
34 pages |
| Authors:
Stewart Reddaway; Pete Rogina; Ken Cameron; Simon McIntosh-Smith; David Stuttard; WORLDSCAPE DEFENSE CO MARLTON NJ
|
| This briefing describes the development of a novel, ultra-high performance next-generation Single-Instruction/Multiple-Data (SIMD) processing architecture originally designed to realize immersive, photo-realistic 3-D simulations. This low-power, Multi-Threaded Array Processor (MTAP) architecture provides for hundreds and ultimately thousands of processing elements, each with optional floating point hardware, to perform data parallel processing on image and signal processing applications as well as for compression, encryption, search, and general sensor processing applications. The technology ... |
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| Network-Based Control, Monitoring and Calibration of Shipboard Sensors |
SEP 2003 |
83 pages |
| Authors:
Eusebio P. DA Silva; NAVAL POSTGRADUATE SCHOOL MONTEREY CA
|
| The objective of this thesis is to develop a new calibration system for analog and smart digital pressure sensors, operable by only one person, and capable of calibrating local and remote sensors connected via RS232 cables, Bluetooth or an 802.11b wireless LAN. It is proposed that the operator uses a portable calibration standard and a tablet PC to conduct the sensor calibration. In order to handle local sensors directly connected ... |
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| The Feasibility of Web-Enabled Digitized Video in a Learning Environment |
SEP 2003 |
57 pages |
| Authors:
Lanier A. Westmoreland; NAVAL POSTGRADUATE SCHOOL MONTEREY CA
|
| Traditional methods of instruction limit a person's ability to gain required knowledge, yet many advanced technologies are not used. The potential is unlimited when digitally videotaping a course. Streamlining video over the Internet (wireless or hardwire), Digital Versatile Disc (DVD), Video Home System (VHS), and other modes of multi-media delivery, many of which are accomplished with little or no coordination, may be the wave of future. The technology and flexibility ... |
|
| Dynamic Channel Allocation |
SEP 2003 |
211 pages |
| Authors:
Andrew D. Kaminsky; NAVAL POSTGRADUATE SCHOOL MONTEREY CA
|
| Dynamic Channel Allocation (DCA) offers the possibility of capturing unused channel capacity by allocating unused resources between competing network nodes. This can reduce or possibly eliminate channels sitting idle while information awaits transmission. This holds potential for increasing throughput on bandwidth constrained networks. This thesis begins by examining channel allocation techniques currently used. Following this, a solution is proposed that utilizes two types of algorithms to dynamically allocate channels from ... |
|
| Compiler Optimizations for Power-Aware Computing. Volume 2 of 2 |
SEP 2003 |
101 pages |
| Authors:
Vincent J. Mooney III; GEORGIA TECH RESEARCH CORP ATLANTA
|
| This final report summarizes work done on the DARPA funded project "Compiler Optimizations for Power Aware Computing." Volume I addresses methodologies invented that can be categorized as software based approaches, hardware based approaches and combined software/hardware based approaches. One of the software based approaches, data remapping, showed a 3.1X energy*delay reduction on a realistic example. One of the hardware based approaches, frequency/voltage scaling of second-level memory, showed a 1.3X energy*delay ... |
|
| Compiler Optimizations for Power-Aware Computing. Volume 1 of 2 |
SEP 2003 |
35 pages |
| Authors:
Vincent J. Mooney III; GEORGIA TECH RESEARCH CORP ATLANTA
|
| This final report summarizes work done on the DARPA funded project "Compiler Optimizations for Power Aware Computing." Volume I addresses methodologies invented that can be categorized as software based approaches, hardware based approaches and combined software/hardware based approaches. One of the software based approaches, data remapping, showed a 3.1X energy*delay reduction on a realistic example. One of the hardware based approaches, frequency/voltage scaling of second-level memory, showed a 1.3X energy*delay ... |
|
| COPPER: Compiler-Controlled On-Demand Approach to Power-Efficient Computing |
SEP 2003 |
18 pages |
| Authors:
Nikil Dutt; Rajesh Gupta; Alex Nicolau; Alex Veidenbaum; CALIFORNIA UNIV IRVINE DEPT OF INFORMATION AND COMPUTER SCIENCE
|
| The goal of this research was to build and demonstrate a capability in hardware (processors-memory) and software for management of power resources, and explore its trade-off against speed, accuracy and throughput requirements. The emphasis of this project was as much on utilization of the most power efficient architectural and software techniques as on their coordinated management across hardware and software levels. Through a coordinated management of power-control knobs from compiler ... |
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| Preliminary Design of ArchE: A Software Architecture Design Assistant |
SEP 2003 |
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| Authors:
Felix Bachmann; Len Bass; Mark Klein; CARNEGIE-MELLON UNIV PITTSBURGH PA SOFTWARE ENGINEERING INST
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| This report presents a procedure for moving from a set of quality attribute scenarios to an architecture design that satisfies those scenarios. This procedure is embodied in a preliminary design for an architecture design assistant named ArchE (Architecture Expert), which will be implemented on a rule-based platform. This report includes the theory and rationale precipitating the design of ArchE and then describes this design in detail. |
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Computer Hardware
