| Nanodevices from Nanocomponents: Memory Logic and Mechanical Nanodevices |
11-May-2009 |
21 pages |
| Authors:
Charles J O'Connor; Jiye Fang; Leonard Spinu; Weilie Zhou; NEW ORLEANS UNIV LA
|
 | The purpose of this report is to document the results of the complete effort for this project, which was to investigate the development of nanodevices from nanoscale components. The project focused on exploring the possibilities of employing nanoparticles and other nanocomponents to fabricate nanodevices. The four main components of the project were: quantum dot memory devices, multilevel logic devices, electromechanical devices, and nanosensor devices. |
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| Scalable Knowledge Discovery Through Grid Workflows |
Apr-2009 |
102 pages |
| Authors:
Yolanda Gil; Jihie Kim; Ewa Deelman; Paul Groth; Gaurang Mehta; Varun Ratnakar; Karan Vahi; UNIVERSITY OF SOUTHERN CALIFORNIA MARINA DEL REY INFORMATION SCIENCES INST
|
| The goal of this effort was to drastically reduce the human effort required to configure and execute new workflows for data analysis from weeks to minutes by eliminating the need for costly human monitoring and intervention. This involves developing end-to-end data analysis systems to analyze data from many different sources and with many different algorithms and analytical tools. Their approach combined three central ideas: 1) workflows with rich representations of ... |
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| Proactive Intelligence (PAINT) Simulated Exploration of Executable Design Strategies (SEEDS) |
Apr-2009 |
28 pages |
| Authors:
Rafael Alonso; Sven Brueckner; Diane Yang; Andrew Yinger; TECHTEAM GOVERNMENT SOLUTIONS INC CHANTILLY VA DIGITAL SUPPORT
|
| The ProActive Intelligence(PAINT) Simulated Exploration of Executable Design Strategies (SEEDS) project first defined the overall systems architecture for the creation of robust, complex, & optimized probes based on a generate & test approach, then specified the architecture & processes within the Possible World Generator, our key component for testing & evaluating probe candidates, & finally, implemented & demonstrated an illustration-of-concept interactive prototype that shows the primary interactions of the key ... |
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| High Performance Computing Innovation Service Portal Study (HPC-ISP) |
Apr-2009 |
27 pages |
| Authors:
Suzy Tichenor; Brian Schott; Robert Graybill; UNIVERSITY OF SOUTHERN CALIFORNIA MARINA DEL REY INFORMATION SCIENCES INST
|
| This project was a study by the Information Sciences Institute (ISI), the Council on Competitiveness (Council), Pratt & Whitney (P&W), Ohio Supercomputer Center (OSC), and Georgetown University (GU) intended to: 1) identify why companies that do not currently employ HPC for advanced modeling and analysis have failed to adopt this technology when the benefits have been showcased so compellingly, and 2) develop technical and business concepts that could help enable ... |
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| High Performance Computing for National Security and Competitive Strength (HPC-NSCS) |
Apr-2009 |
14 pages |
| Authors:
Suzy Tichenor; Brian Schott; Cynthia McIntyre; UNIVERSITY OF SOUTHERN CALIFORNIA MARINA DEL REY
|
| The goal of this effort was to stimulate and facilitate wider usage of high performance computing (HPC) across the private sector to propel productivity, innovation, and competitiveness. The council on Competitiveness (Council) confirmed 14 industrial / 1 Museum executives to give presentations at SC07, the annual international supercomputing conference to be held November 12-16, 2007. Presentations focused on how their organizations are using high performance computing to drive competitive advantage. ... |
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| Asymmetric Core Computing for U.S. Army High-Performance Computing Applications |
Apr-2009 |
32 pages |
| Authors:
Lam Nguyen; Dale Shires; Brian Henz; Song Jun Park; Jerry Clarke; Kelly Kirk; ARMY RESEARCH LAB ABERDEEN PROVING GROUND MD COMPUTATIONAL AND INFORMATION SCIENCES DIR
|
| High-performance computing (HPC) is in a state of transition. HPC users have traditionally relied upon two things to supply them with processing power: speed of the central processing units (CPUs) and the scalability of the system. There are problems with this approach. Physical limitations are curtailing clock speed increases in general-purpose CPUs, the von Neumann load-execute-store approach does not map well to every computational problem, and systems of thousands of ... |
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| Analysis of Trimble Mini-T GPS Receiver |
31-Mar-2009 |
13 pages |
| Authors:
Richard M White; John P McConnell; Daniel S Newton; NAVAL RESEARCH LAB WASHINGTON DC
|
| This report summarizes the function, capability, and I/O of the Trimble Mini-T GPS receiver (officially known as the Trimble Mini-T GPS Disciplined Clock Module; P/N 57303-05). The primary objective of this report is to document the intricacies of the Mini-T beyond the scope of its user manual, for the purpose of future integration of the Mini-T into larger, GPS-based systems. A detailed analysis on the input and output of the ... |
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| Characterizing Component Hiding Using Ancestral Entropy |
26-Mar-2009 |
201 pages |
| Authors:
Jason A Williams; AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH DEPT OF ELECTRICAL AND COMPUTER ENGINEERING
|
| In this research, the problem of software protection and the attributes that define that protection is considered. Specifically, how to protect programs defined as structural combinational logic gates. Obfuscation is one technique for protecting such circuits and involves replacing an original circuit with a functionally equivalent variant that has some definable hiding property. The difficulty of reverse engineering versus identifying and recovering the original components or sub-circuits within an original ... |
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| Program Management Issues with Fielding, Resetting Digital Systems |
24-Mar-2009 |
30 pages |
| Authors:
Rod Mentzer; ARMY WAR COLL CARLISLE BARRACKS PA
|
| Army transformation and the requirement to support two major combat operations simultaneously has placed a burden on the Army's ability to generate equipped, trained, and ready combat power on a reliable non-exhaustive cyclic model. The Army Force Generation Model (ARFORGEN) has done a great deal to alleviate that stress by dictating timelines for equipping, training, deploying, and resetting of combat units. However, when dealing with information systems that have an ... |
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| New Theory and Algorithms for Compressive Sensing |
06-Mar-2009 |
17 pages |
| Authors:
Richard G Baraniuk; RICE UNIV HOUSTON TX
|
| In this project we expanded the field of compressive sensing in both theoretical and practical ways. We first demonstrated the information scalability of CS. We applied CS principles to analog-to-digital conversion, showing ADC can be accomplished on structured high rate signals with sub-Nyquist sampling. We introduced a smashed filter to perform statistical classification problems with a rate of measurements that corresponds to the problem structure, rather than bandwidth. Second, we ... |
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| Defense Science Board Report on Advanced Computing |
Mar-2009 |
65 pages |
| Authors:
Bruce Tarter; Robert Nesbit; DEFENSE SCIENCE BOARD WASHINGTON DC
|
| This is the final report of the DSB Task Force on NNSA's Strategic Plan for Advanced Computing, co-chaired by Dr. Bruce Tarter and Mr. Robert Nesbit. The Task Force was asked to evaluate NNSA's strategic plan for Advanced Simulation and Computing (ASC) and its adequacy to support the Stockpile Stewardship Program (SSP), whose mission is to ensure the safety, performance and reliability of our Nation's nuclear weapons stockpile. The Task ... |
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| A Framework for Automated Digital Forensic Reporting |
Mar-2009 |
109 pages |
| Authors:
Farrell; Paul F Jr; NAVAL POSTGRADUATE SCHOOL MONTEREY CA
|
| Forensic analysis is the science of finding, examining and analyzing evidence in support of law enforcement, regulatory compliance or information gathering. Today, almost all digital forensic analysis is done by humans, requiring dedicated training and consuming man-hours at a considerable rate. As storage sizes increase and digital forensics gain importance in investigations, the backlog of media requiring human analysis has increased as well. This thesis tests today's top-of-the-line commercial and ... |
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| Radar Imaging with a Network of Digital Noise Radar Systems |
Mar-2009 |
168 pages |
| Authors:
Ashley L Schmitt; AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH SCHOOL OF ENGINEERING AND MANAGEMENT
|
| Due to the threat of terrorism, today's enemy can be anyone and they can exist anywhere even in populated cities. Monitoring human activities in an urban environment is a difficult problem due walls, clutter, and other obstructions. This thesis discusses the development of a network of digital noise radars that operate simultaneously to track humans and non-human targets inside rooms and through walls. Each individual noise radar works by cross ... |
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| Designing an Ultrasonic Modem for Robotic Communications |
Mar-2009 |
26 pages |
| Authors:
Justin Shumaker; ARMY RESEARCH LAB CLEVELAND OH VEHICLE TECHNOLOGY DIRECTORATE
|
| An ultrasonic modem is a device that can transmit information acoustically. One was designed for the 2008 FIRST Robotics League competition to provide short-range communications with the robot. The creation of this device was the result of a regulation that inhibited any use of electromagnetic-based communications technology in the competition. The ultrasonic modem consists of easily attainable and low-cost parts and was designed to attenuate ambient noise in the audible ... |
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| Unified Behavior Framework in an Embedded Robot Controller |
Mar-2009 |
67 pages |
| Authors:
Stephen S Lin; AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH DEPT OF ELECTRICAL AND COMPUTER ENGINEERING
|
| Recent technological advances produce small, inexpensive, embedded hardware platforms that are powerful enough to match robots from just a few years ago. The Unified Behavior Framework is a flexible, responsive control architecture that has not been applied on embedded systems in robots. This thesis presents a development of the Unified Behavior Framework on the Mini-WHEGSTM, a biologically inspired, embedded robotic platform, which is a small robot that utilize wheel-legs to ... |
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| Interrupt Driven RS-232, Pulse Width Modulation, and Control Processing on a Single 8-bit PIC Chip |
Mar-2009 |
22 pages |
| Authors:
Justin Shumarker; ARMY RESEARCH LAB ABERDEEN PROVING GROUND MD VEHICLE TECHNOLOGY DIRECTORATE
|
| Autopilots utilizing a single processor allow for smaller, lighter, more cost-effective designs than those using multi-processor architecture. Presented here is a software architecture that allows multiple tasks to operate in a real-time mutually exclusive environment using a single 8-bit processor. This type of architecture will be utilized to create an autopilot using a single processor and sensors. The problem is preventing individual tasks from interfering with one another in a ... |
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| An Optimization Framework Based on Domain Decomposition and Model Reduction |
27-Feb-2009 |
21 pages |
| Authors:
Matthias Heinkenschloss; Danny C Sorensen; RICE UNIV HOUSTON TX DEPT OF COMPUTATIONAL AND APPLIED MATHEMATICS
|
| This collaborative research has developed rigorous mathematical and computational frameworks for reduced order model (ROM) generation and the use of ROMs in real-time, design, control, and probabilistic applications of relevance to the Air Force. This research has provided theoretical analyses and numerical studies for several new/extensions of existing ROM approaches, such as goal-oriented, model-constrained approach, balanced truncation model reduction (BTMR) of descriptor systems, and the integration of domain decomposition and ... |
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| Border Searches of Laptop Computers and Other Electronic Storage Devices |
30-Jan-2009 |
13 pages |
| Authors:
Anna C Henning; Yule Kim; LIBRARY OF CONGRESS WASHINGTON DC CONGRESSIONAL RESEARCH SERVICE
|
| As a general rule, the Fourth Amendment of the U.S. Constitution requires government-conducted searches and seizures to be supported by probable cause and a warrant. Federal courts have long recognized that there are many exceptions to this presumptive warrant requirement, one of which is the border search exception. The border search exception permits government officials, in most routine circumstances, to conduct searches based on no suspicion of wrongdoing whatsoever. On ... |
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| The Prospects for Increasing the Reuse of Digital Training Content |
Jan-2009 |
144 pages |
| Authors:
Matthew W Lewis; Michael G Shanley; Susan G Straus; Jeff Rothenberg; Lindsay Daugherly; RAND CORP SANTA MONICA CA
|
| Distributed learning (DL) offers the promise of self-paced learning and training at any time and in any place, as well as new technologies for developing and delivering content and tracking student performance. Although demand for DL is increasing, DL still represents a small percentage of all learning and training, in part because of the high cost of developing and maintaining electronic-learning (e-Learning) materials. Development costs for DL might be reduced ... |
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| Testing and Evaluation of a Pen Input Device Using an Inertial/Magnetic Sensor Module |
Dec-2008 |
81 pages |
| Authors:
Leonidas Drakopoulos; NAVAL POSTGRADUATE SCHOOL MONTEREY CA
|
| In this thesis, the feasibility of developing a pen input device using an inertial/magnetic sensor module is investigated. The emphasis is on testing and evaluation of algorithms for computing handwriting trajectories based on accelerometer measurement data. This research starts by placing the inertial/magnetic sensor in a 2-D plane and writing alphanumeric characters. Before continuing to evaluate the 3-D writing, a calibration algorithm is implemented for computing the length between the ... |
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| Data Acquisition from Volatile Memory: A Memory Acquisition Tool for Microsoft Windows Vista |
Dec-2008 |
127 pages |
| Authors:
Cheong C W Vincent; NAVAL POSTGRADUATE SCHOOL MONTEREY CA
|
| The focus of this research is on extracting data from the volatile random access memory (RAM) on a personal computer running Microsoft's Windows Vista operating system, while minimally affecting the existing data. The projected work includes the development of a kernel-mode device driver with the capabilities on one or more versions of Microsoft Windows Vista, a user-mode application that interacts with the driver, usage documentation and outcome of the research. ... |
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| Information Storage and Processing in Rydberg Atoms |
Dec-2008 |
9 pages |
| Authors:
Robert R Jones; VIRGINIA UNIV CHARLOTTESVILLE RECTOR AND VISTORS OF THE UNIVERSITY OF VIRGINIA
|
| Experiments performed under this grant were designed to exploit the extreme electric field sensitivity of highly-excited Rydberg atoms to test methods for asserting coherent control over inter- and intra-atomic dynamics. The work focused on the application of Rydberg wavepacket techniques to investigate information storage and processing within model quantum systems. New methods for manipulating and probing quantum dynamics in Rydberg atoms were developed and used to read and write information ... |
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| On Large-Scale Hybrid Computing Architecture for Neocortical Models - With an Application in Realizing Cognizance Operations of the Visual Cortex |
Nov-2008 |
32 pages |
| Authors:
Qing Wu; Qinru Qiu; STATE UNIV OF NEW YORK AT BINGHAMTON
|
| This report describes working hardware and software developed to realize large-scale Brain-State-in-a-Box (BSB) models on a workstation with hardware acceleration using a Field Programmable Gate Array (FPGA). Just one Xilinx XC2VP70 FPGA was able to support about 600 128-dimensional BSB models to run at 10ms reaction time. Software was developed that controls the hardware operations and sends/receives data through publish/subscribe routines provided by an open-source package. Next, the confabulation based ... |
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| Bio/Nano Electronic Devices and Sensors |
Oct-2008 |
11 pages |
| Authors:
W K Jones; FLORIDA INTERNATIONAL UNIV MIAMI DIV OF SPONSORED RESEARCH AND TRAINING
|
| This effort consists of five research thrusts: (1) Dense Memory Devices-(1)3-D magnetic recording was enhanced using patterned soft underlayers and interlayer, (2) Cold cathode microwave generator and ceramic electron multiplier-ceramic multiplier using a novel secondary electron yield materials of MgO and CNT was demonstrated as well as cooling structures based on capillary cooling.(3) CNT-based Bio-nano Sensor single walled CNT structures with FIB generated nanogaps have been used to probe single ... |
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| Exploration of a Research Roadmap for Application Development and Execution on Field-Programmable Gate Array (FPGA)-Based Systems |
Oct-2008 |
45 pages |
| Authors:
Esam El-Araby; Greg Stitt; Melissa Smith; Proshanta Saha; Saumil Merchant; Herman Lam; Ivan Gonzalez; Alan D George; Tarek El-Ghazawi; Nahid Alam; GEORGE WASHINGTON UNIV WASHINGTON DC
|
| FPGA-based reconfigurable computing (RC) technology has been widely used by the DoD community to exploit performance, power, area, cost, and versatility. Significant challenges, however, remain in application development tools and design methodologies. This study focuses on investigating key challenges and limitations of FPGA tools, and identifying and assessing potential solutions and research areas. The investigation included three major tasks: a) survey of use cases and the state of existing tools; ... |
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| Analysis and Defense of Vulnerabilities in Binary Code |
29-Sep-2008 |
156 pages |
| Authors:
David Brumley; CARNEGIE-MELLON UNIV PITTSBURGH PA SCHOOL OF COMPUTER SCIENCE
|
| In this thesis, we develop techniques for vulnerability analysis and defense that only require access to vulnerable programs in binary form. Our approach does not use or require source code. We focus on a binary-centric approach since everyone typically has access to the binary code for the programs they run. Thus, our approach is applicable to a wider audience than previous approaches that require or utilize source code. In addition, ... |
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| Fault Tolerant Microcontroller for the Configurable Fault Tolerant Processor |
01-Sep-2008 |
225 pages |
| Authors:
Swiggins; David Jr; NAVAL POSTGRADUATE SCHOOL MONTEREY CA
|
| In this thesis, the design of a fault tolerant microcontroller for the Configurable Fault Tolerant Processor is presented. The Configurable Fault Tolerant processor is a spaceborne Field Programmable Gate Array experiment platform susceptible to Single Event Upsets. Fault tolerance is needed to control the experiment in higher radiation orbits and the microcontroller will offer enhanced functionality for experiments. The 16-bit microcontroller is contained within the resources of a single Field ... |
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| Development of a Distributed Digital Array Radar (DDAR) |
01-Sep-2008 |
180 pages |
| Authors:
Pontus Djerf; Ioannis Tornazakis; NAVAL POSTGRADUATE SCHOOL MONTEREY CA GRADUATE SCHOOL OF BUSINESS AND PUBLIC POLICY
|
| Distributed digital arrays have many potential applications in radar and communication systems. The objective of this thesis is to re-examine previous research on distributed digital array radar (DDAR) and evaluate several critical aspects of a proposed wireless architecture. Self-standing transmit/receive (T/R) modules are synchronized wirelessly. An important issue addressed in this thesis is whether a simple low-cost synchronization circuit would perform adequately. To this end two breadboard T/R modules were ... |
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| Development of a 3-D Pen Input Device |
01-Sep-2008 |
53 pages |
| Authors:
Deven A Rhett; NAVAL POSTGRADUATE SCHOOL MONTEREY CA
|
| The principal objective of this research is to demonstrate the capability of obtaining the acceleration in the navigation frame of a unistroke which can be written on any surface or in the air while correcting integration errors from the measurements of the IMU (Inertial Measurement Unit) of the pen-type input devices. With the core topic of obtaining the acceleration while correcting integration errors, there are four subsidiary research questions relating ... |
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| Verification using Satisfiability Checking, Predicate Abstraction, and Craig Interpolation |
Sep-2008 |
297 pages |
| Authors:
Himanshu Jain; CARNEGIE-MELLON UNIV PITTSBURGH PA SCHOOL OF COMPUTER SCIENCE
|
| Automatic verification of hardware and software implementations is crucial for computer systems. This thesis develops new techniques for building efficient decision procedures and adds new capabilities to existing decision procedures. Most SAT solvers require the input formula to be in Conjunctive Normal Form (CNF). However, typical formulas that arise in practice are not in CNF. Converting a general formula to CNF introduces overhead in the form of new variables and ... |
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| Tera-OP Reliable Intelligently Adaptive Processing System (TRIPS) Implementation |
Sep-2008 |
108 pages |
| Authors:
Stephen W Keckler; Doug Burger; Kathryn S McKinley; Steve Crago; Richard Lethin; TEXAS UNIV AT AUSTIN DEPT OF COMPUTER SCIENCES
|
| The Tera-op Reliable Intelligently Adaptive Processing System (TRIPS) is a novel computer system designed to address technology scaling challenges, to provide high performance through concurrency, and to demonstrate mechanisms for hardware polymorphism. The team has constructed a full-system TRIPS prototype including a new Explicit Data Graph Execution (EDGE) instruction set architecture, custom application-specific integrated circuit (ASIC) chips, system circuit boards, a custom compiler with new optimization capabilities, a software development ... |
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| The Effect of Size Distribution on the Switching Field Distribution of Co/Pd Multilayered Nanostructure Arrays |
Aug-2008 |
3 pages |
| Authors:
Dmitri Litvinov; Darren Smith; James Rantschler; Paul Ruchhoeft; Sakhrat Khizroev; HOUSTON UNIV TX CENTER FOR NANOMAGNETIC SYSTEMS
|
| We use Ion Beam Proximity Lithography (IBPL) to produce 4mm x 4mm arrays of 220 nm dots in perpendicularly-oriented Co/Pd multilayered media. IBPL is used to reduce the size distribution sigmaD of the arrays, and subsequently He+ ion irradiation is used to reduce their anisotropy. The Switching Field Distribution sigma(Hcr)/H(Cr) is measured for each sample before and after irradiation, and a linear relationship is experimentally found between sigma(Hcr)/H(Cr) and sigmaD. ... |
|
| Terascale Cluster for Advanced Turbulent Combustion Simulations |
25-Jul-2008 |
8 pages |
| Authors:
Stephen B Pope; Steven R Lantz; CORNELL UNIV ITHACA NY
|
| A terascale computing system was purchased and brought into full operation. The main cluster consisted of 36 dual-dual-core Dell servers connected by a QLogic InfiniBand switch. The full system included 2 interactive servers holding 2 terabytes of file storage. The cluster enabled combustion simulations to run on up to 140 processor cores. On benchmarking tests with HP Linpack, the system was found to perform well, achieving 1.15 teraflop/s, or 68.7% ... |
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| Information and Communications Technology and the Global Marketplace |
01-Jul-2008 |
5 pages |
| Authors:
Mitchell Komaroff; OFFICE OF THE ASSISTANT SECRETARY OF DEFENSE FOR NETWORKS AND INFORMATION INTEGRATION WASHINGTON DC
|
| The global information and communications technology (ICT) marketplace brings innumerable benefits to the U.S. Government and the Department of Defense (DoD). However, this extended and often unknown supply chain has created an environment where trustworthiness in commercial ICT products is no longer implicit, requiring the U.S. Government to expand its understanding of Information Assurance (IA). In this new environment, employing comprehensive protection mechanisms requires consideration of both the depth and ... |
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| High Productivity Computing Systems for Command and Control |
01-Jun-2008 |
25 pages |
| Authors:
Christopher Flynn; Scott Spetka; STATE UNIV OF NEW YORK INST OF TECHNOLOGY AT UTICA DEPT OF COMPUTER SCIENCE
|
| The most significant issue underlying all future command and control (C2) architectures is the ability to develop software that can harness the next generation of processors. Multicore processors, scaling into thousands of processors per chip will soon be prevalent in all C2 systems. The success of C2 systems will depend on our ability to adapt to the new processor technology. Existing C2 systems that implement scientific codes for image processing ... |
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| Comparing Throughput and Power Consumption in Sequential and Reconfigurable Processors |
05-May-2008 |
85 pages |
| Authors:
Kevin K Liu; NAVAL ACADEMY ANNAPOLIS MD
|
| This research project involves an investigation of parallel processing using reconfigurable logic devices. The goal of this project is to support the Naval Research Labs' recent acquisition of a Cray XD-1 supercomputer. A feature of the Cray XD-1 is that it contains field programmable gate arrays (FPGAs). These reconfigurable devices contain hardware whose connections can be modified to target a specific computation. This adaptability can significantly improve the processing speed ... |
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| Open Architecture, Inventory Pooling and Maintenance Modules |
May-2008 |
24 pages |
| Authors:
Geraldo Ferrer; NAVAL POSTGRADUATE SCHOOL MONTEREY CA GRADUATE SCHOOL OF BUSINESS AND PUBLIC POLICY
|
| OPEN ARCHITECTURE: Combines the benefits of commonality and modularity in product design: If two suppliers design a component with same functionality, both must adopt the same interface with the main product. - Internal design may be different. - Usually adopted in software design. - May also be adopted in physical products. HENCE: Product aggregation (through Open Architecture) may provide the same demand pooling benefit as Place aggregation! - Even greater ... |
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| Which Unchanged Components to Retest After a Technology Upgrade |
23-Apr-2008 |
36 pages |
| Authors:
Valdis Berzins; NAVAL POSTGRADUATE SCHOOL MONTEREY CA DEPT OF COMPUTER SCIENCE
|
| The Navy's open architecture framework is intended to promote reuse and reduce costs. This paper focuses on exploiting open architecture principles to reduce testing effort and costs in cases in which the requirements and code for a subsystem have not been changed, but the code is running on new hardware and/or new operating systems due to a technology advancement upgrade. This situation is common in Navy and DoD contexts such ... |
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| Share Repository Framework: Component Specification and Otology |
23-Apr-2008 |
38 pages |
| Authors:
Curtis Blais; Jean Johnson; NAVAL POSTGRADUATE SCHOOL MONTEREY CA DEPT OF SYSTEMS ENGINEERING
|
| Data sharing is the information technology watchword of our time. Revolutions in information exchange and interoperability are underway in government and industry through policies on the strategic end to data standards on the implementation end. The revolution is transforming acquisition systems and processes through specification of open architectures, which enables construction of new complex systems from crafted components. In August 2006, Program Executive Officer, Integrated Warfare Systems (PEO IWS), established ... |
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| Verification, Validation, and Accreditation (VV&A) of Federations (Verification, validation et accreditation (VV&A) des federations) |
01-Apr-2008 |
104 pages |
| Authors:
NATO RESEARCH AND TECHNOLOGY ORGANIZATION NEUILLY-SUR-SEINE (FRANCE)
|
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| Real World Cognitive Multi-Tasking and Problem Solving: A Large Scale Cognitive Architecture Simulation Through High Performance Computing-Project Casie |
01-Mar-2008 |
41 pages |
| Authors:
Nael Abu-Ghazaleh; Kiley McEvoy; Vinay Kolar; Mark Zhang; Zhen Guo; Santos; Eugene Jr; DARTMOUTH COLL HANOVER NH
|
| In its grandest sense, Project CASIE explored the development of a computational system capable of high level perception and problem solving that reflects the cognitive processes of the human brain. Most specifically, it concentrated on better understanding and modeling intuition and insight in a computational fashion. The goal was to address the fundamental problem of modeling and solving communities of tasks from a cognitive point of view through multiple problem ... |
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| Digital Fingerprinting of Field Programmable Gate Arrays |
01-Mar-2008 |
87 pages |
| Authors:
James W Crouch; AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH GRADUATE SCHOOL OF ENGINEERING AND MANAGEMENT
|
| Commercial off-the-shelf (COTS) component usage is becoming more prevalent in military applications due to current Department of Defense (DoD) policies. The easy accessibility of COTS will give reverse engineers a higher probability of successfully tampering, coping, or reverse engineering circuits that contain critical capabilities. To prevent this and verify the trustworthiness of hardware, circuit identification tags or serials numbers can be used. However, these values can be easily obtained and ... |
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| SHI(EL)DS: A Novel Hardware-Based Security Backplane to Enhance Security with Minimal Impact to System Operation |
01-Mar-2008 |
139 pages |
| Authors:
Matthew G Judge; AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH GRADUATE SCHOOL OF ENGINEERING AND MANAGEMENT
|
| Computer security continues to increase in importance both in the commercial world and within the Air Force. Dedicated hardware for security purposes presents and enhances a number of security capabilities. Hardware enhances both the security of the security system and the quality and trustworthiness of the information being gathered by the security monitors. Hardware reduces avenues of attack on the security system and ensures the trustworthiness of information only through ... |
|
| Department of Defense High Performance Computing Modernization Program. 2007 Annual Report |
01-Mar-2008 |
113 pages |
| Authors:
HIGH PERFORMANCE COMPUTING MODERNIZATION PROGRAM ARLINGTON VA
|
| For more than a decade, the HPCMP has supported a workforce that routinely uses HPC resources to solve many of the Department's most challenging scientific and engineering problems. This, in turn, helps the United States ensure military advantage and warfighting superiority on the 21st century battlefield. The Program enables scientists and engineers to further the Department's objectives through research, development, test, and evaluation (RDT&E) activities that support science and technology ... |
|
| Implementation and Scalability of a Pure Java Parallel Framework with Application to Hyperbolic Conservation Laws (Preprint) |
04-Feb-2008 |
21 pages |
| Authors:
Jean-Luc Cambier; Michael Kapper; AIR FORCE RESEARCH LAB EDWARDS AFB CA PROPULSION DIRECTORATE
|
| We introduce a pure Java parallel framework for Single Process, Multiple Dataset (SPMD) applications, intended for time-accurate solutions of hyperbolic conservation laws. The software architecture is based upon an extension of the client-server paradigm, utilizing a tree database abstraction and allowing for multi-tiered network configurations. The framework is designed to be hardware independent, with the ability to handle both shared-memory and distributed-memory hardware alike, allowing execution over heterogeneous networks. Task ... |
|
| Polymorphous Computing Architectures |
12 DEC 2007 |
95 pages |
| Authors:
Mark Horowitz; STANFORD UNIV CA COMPUTER SYSTEMS LAB
|
| We describe the architecture and hardware implementation of a coarse grain parallel computing system with flexibility in both memory and processing elements. The memory subsystem supports a wide range of programming models efficiently, including cache coherency, message passing, streaming, and transactions. The memory controller implements these models using metadata stored with each memory block. Processor flexibility is provided using Tensilica Xtensa cores. We use Xtensa processor options and Tensilica Instruction ... |
|
| SecureCore Software Architecture: Trusted Path Application (TPA) Requirements |
DEC 2007 |
32 pages |
| Authors:
Paul C. Clark; Cynthia E. Irvine; Timothy E. Levin; Thuy D. Nguyen; Timothy M. Vidas; NAVAL POSTGRADUATE SCHOOL MONTEREY CA CENTER FOR INFORMATION SYSTEMS SECURITY STUDIES AND RESEARCH
|
| A mobile computing device has more inherent risk than desktops or most other stationary computing devices. Such mobile devices are typically carried outside of a controlled physical environment, and they must communicate over an insecure medium. The risk is even greater if the data being stored, processed and transmitted by the mobile device is classified. The purpose of the SecureCore research project is to investigate fundamental architectural features required for ... |
|
| Paperless Policy: Digital Filing System Benefits to DoD Contracting Organizations |
DEC 2007 |
127 pages |
| Authors:
Brad J. Sherman; Eric Freeman; NAVAL POSTGRADUATE SCHOOL MONTEREY CA
|
| The year 2000 was the cutoff date for the Department of Defense (DoD) to have paperless processes in place. Since then, advances in computer technology have led to such paperless contracting processes as the DoD-wide Standard Procurement System (SPS), Wide Area Work Flow, and other department-specific major weapon procurement information systems. Although great strides were made by the DoD to implement paperless contracting processes, there still exists substantial room for ... |
|
| Magnetic Random Access Memory for Embedded Computing |
29 OCT 2007 |
212 pages |
| Authors:
Gregory W. Donohoe; IDAHO UNIV MOSCOW DEPT OF ELECTRICAL ENGINEERING
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| The goal of this research was to develop an embedded magnetic memory technology to be integrated into Complementary Metal Oxide Semiconductor (CMOS) integrated circuit fabrication process to provide radiation-hard, logic elements and small random-access memories. The goal is not to provide large scale, bulk memory, but latches and flip flops that serve as state and data registers for sequential logic, and configuration registers for configurable logic. The benefits to spacecraft ... |
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| Software Architecture: Managing Design for Achieving Warfighter Capability |
12 OCT 2007 |
57 pages |
| Authors:
Brad Naegle; Diana Petross; NAVAL POSTGRADUATE SCHOOL MONTEREY CA GRADUATE SCHOOL OF BUSINESS AND PUBLIC POLICY
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| This research analyzes the problems associated with poorly performing DoD software-intensive systems focusing on the critical software architectural design process. DoD's software-intensive systems continue to experience software related performance supportability and security shortfalls resulting in system software failures costly and resource-intensive support requirements and security vulnerabilities that negatively impact the warfighter missions. As software performance is significantly determined by the software architecture this research examined current practices for controlling and ... |
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Computer Hardware
