The research and development problem we have investigated in this project is the VLSI implementation of fast and highly parallel algorithms based on one-line arithmetic. The on-line approach is characterized by simple interconnection requirements and digit-level pipelining suitable for highly concurrent special-purpose VLSI designs. The objective of the project was to evaluate the feasibility and efficiency of on-line approach in NMOS and CMOS VLSI implementations
For convenience we summarize here the project objectives as stated in the research proposal. This research in the methodologies for the specification and design of high-speed, fault-tolerant VLSI array structures has two related objectives (1) a high-level language approach to the specification and simulation of VLSI algorithms and networks using a functional-style (LISP-like) language (Task 1), and (2) cost-effective methods to introduce fault-tolerance (error detection, fault location, retry, and reconfiguration) ...
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