A highly-configurable analog system is presented. A prototype chip is fabricated and an ADC and filter functionalities are demonstrated. The chip consists of eight identical programmable stages. In an ADC configuration, the first five stages are programmed to implement a 10- bit ADC. The ADC has ENOB of 8 bits at 50 MSPS. The ENOB improves to 8.5 bits if the sampling rate is lowered to 30 MSPS. The ADC ...
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