The current conduction process through a nanowire wrap-around-gate, ~50 nm channel diameter, silicon MOSFET has been investigated and compared with a ~2 mum wide slab, ~200 nm thick silicon (SOI) top-only-gate planar MOSFET with otherwise similar doping profiles, gate length and gate oxide thickness. The experimental characteristics of the nanowire and planar MOSFETs were compared with theoretical simulation results based on semiempirical carrier mobility models. The SOI nanowire MOS devices ...
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