| A Fast Multiport Memory Based on Single-Port Memory Cells |
10 JUL 91 |
15 pages |
| Authors:
Ronald L. Rivest; Lance A. Glasser; MASSACHUSETTS INST OF TECH CAMBRIDGE LAB FOR COMPUTER SCIENCE
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 | We present a new design for dual-port memories that uses single-port memory cells but guarantees fast deterministic read/write access. The basic unit of storage is the word, rather than the bit, and addressing conflicts result in bit errors that are removed by correction circuitry. The addressing scheme uses Galois field arithmetic to guarantee that the maximum number of bit errors in any word accessed is one. These errors can be ... |
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| Critical Problems in Very Large Scale Computer Systems |
31 MAR 88 |
89 pages |
| Authors:
Paul Penfield Jr.; Anant Agarwal; William J. Dally; Lance A. Glasser; Thomas F. Knight Jr; MASSACHUSETTS INST OF TECH CAMBRIDGE MICROSYSTEMS RESEARCH CENTER
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| This is the first semiannual report on this contract. The purpose of the present contract is to investigate limiting technologies for a very large computer system, one which, if built during the mid 1990's, would be so large that the nation could only afford one or two of them. The purpose of this contract is to investigate plausibility, which is defined as the step before feasibility. Once plausibility is demonstrated, ... |
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| A Coherent VLSI Environment |
31 MAR 87 |
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| Authors:
Paul Penfield Jr.; William J. Dally; Lance A. Glasser; Thomas F. Knight Jr.; F. T. Leighton; MASSACHUSETTS INST OF TECH CAMBRIDGE MICROSYSTEMS RESEARCH CENTER
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 | It is important to know how fast a rise time can be achieved, or at what frequencies unwanted oscillations might occur. A set of necessary and sufficient bounds are now possible, in the sense that every point in the s-plane can be easily discovered to be either a frequency at which oscillation cannot occur with any possible combination of components and ideal transformers, or else a point at which a ... |
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| A Coherent VLSI Design Environment |
31 MAR 87 |
85 pages |
| Authors:
Paul Penfield Jr.; William J. Dally; Lance A. Glasser; Thomas F. Knight Jr.; F. T. Leighton; MASSACHUSETTS INST OF TECH CAMBRIDGE MICROSYSTEMS RESEARCH CENTER
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| It has been an open question in electrical network theory whether it is possible to synthesize a network with a prescribed natural frequency (in the complex s-plane) out of a restricted class of components. It was possible to say since the 1950s that no natural frequencies can be obtained in certain parts of the s-plane, but not the converse, namely that at other points a circuit can be devised. This ... |
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| RELIC: A Reliability Simulator for Integrated Circuits |
JAN 87 |
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| Authors:
Teresa S. Hohol; Lance A. Glasser; MASSACHUSETTS INST OF TECH CAMBRIDGE RESEARCH LAB OF ELECTRONICS
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| Many of the failure mechanisms which cause reliability problems in VLSI chips can be influenced or avoided in the circuit design phase. RELIC is a reliability simulator developed to analyze and predict the stress and wear on MOS VLSI chips due to such mechanisms. RELIC uses a simple methodology for abstracting the idea of the stress from any particular failure mechanism, thus allowing analyses of many different failure mechanisms. There ... |
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| A Coherent VLSI Design Environment |
30 SEP 86 |
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| Authors:
Paul Penfield Jr.; William J. Dally; Lance A. Glasser; Thomas F. Knight Jr.; Charles E. Leiserson; MASSACHUSETTS INST OF TECH CAMBRIDGE MICROSYSTEMS RESEARCH CENTER
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| The CAD frame Schema has been outfitted with a uniform protocol or aggregate data structures, which includes new control structures for examining and searching through the data structures. Circuit simulators installed in Schema can now use their own scratchpad, and call a variety of tools to deal with the pertinent data structures. Waveform bounding results are now beginning to be available for ECL circuits, similar to those reported earlier for ... |
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| Methodology Verification of Hierarchically Described VLSI Circuits |
JUN 86 |
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| Authors:
Isaac L. Bain; Lance A. Glasser; MASSACHUSETTS INST OF TECH CAMBRIDGE LAB FOR COMPUTER SCIENCE
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| The standard approach to master the complexity of designing VLSI systems is to adopt a set of rules that, when respected, are conducive to correct implementations. Any such collection of rules can be called a design methodology. Most of the effort in computer-aided VLSI methodology verification has been traditionally concentrated on geometrical DRC. This paper describes a program that checks circuit conformity to other kinds of rules. This is done ... |
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| Macromodeling and Optimization of Digital MOS VLSI Circuits |
MAR 86 |
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| Authors:
Mark D. Matson; Lance A. Glasser; MASSACHUSETTS INST OF TECH CAMBRIDGE RESEARCH LAB OF ELECTRONICS
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| Power consumption and signal delay are crucial to the design of high- performance VLSI circuits. This paper presents CAD tools for modeling and optimizing digital MOS designs. The tools determine the transistor sizes that minimize circuit power consumption subject to constraints on signal path delays. Computational efficiency is obtained through macromodeling techniques and a specialized optimization algorithm. The macromodels are based on device equations, and encapsulate logic gate behavior in ... |
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| Synthesis of a Self-Timed Controller for a Successive-Approximation A/D Converter |
OCT 85 |
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| Authors:
Tam-Anh Chu; Lance A. Glasser; MASSACHUSETTS INST OF TECH CAMBRIDGE DEPT OF ELECTRICAL ENGINEERING AND COMPU TER SCIENCE
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| This paper documents the procedure for designing a self-timed controller for a successive-approximation A/D converter. From the functional specification, a Signal Transition Graph is constructed to describe the operation of the control circuit. This graph is then modified into a well-formed graph. Such a graph can be transformed into a deadlock-free and hazard-free implementation directly. The structure of the control circuit and the logic equations are then derived directly from ... |
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| Synchronizer Failure in A/D Converters |
OCT 85 |
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| Authors:
Lance A. Glasser; MASSACHUSETTS INST OF TECH CAMBRIDGE RESEARCH LAB OF ELECTRONICS
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| Analog-to-digital converters that must produce a valid output in a specified period of time are subject to synchronizer failure. Three types of A/D converters are examined: flash converters, clocked successive approximation converters, and self-timed successive approximation converters. Lower bounds on their worst-case conversion time as a function of the fault probability are derived. |
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| A Coherent VLSI Design Environment |
30 SEP 85 |
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| Authors:
Paul Penfield Jr.; Lance A. Glasser; Thomas F. Knight Jr.; Charles E. Leiserson; Ronald L. Rivest; MASSACHUSETTS INST OF TECH CAMBRIDGE DEPT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE
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| This report covers the period from April 1, 1985 through September 30, 1985. The research discussed here is described in more detail in several published and unpublished reports cited. The CAD frame Schema has progressed to the point where it is useful for ample chip designs. The interface to CIF is complete, and work has begun on importing layout libraries. An interface to EDIF is being installed. Simulators can now ... |
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| The Waveform Bounding Approach to Timing Analysis of Digital MOS IC's |
NOV 83 |
6 pages |
| Authors:
John L. Wyatt Jr.; Charles Zukowski; Lance A. Glasser; Paul Bassett; Paul Penfield Jr; MASSACHUSETTS INST OF TECH CAMBRIDGE RESEARCH LAB OF ELECTRONICS
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| The waveform bounding approach to fast timing analysis of MOS VLSI circuits is discussed. The idea is to compute rigorous closed-form expressions giving upper and lower bounds for transient voltage waveforms, rather than exact values. The goal is to enable rapid computation without sacrificing user confidence in the results. (RRH) |
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| Theory and Practice for Large-Scale Systems |
83 |
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| Authors:
Paul Penfield Jr.; Dimitri A. Antoniadis; Clifton G. Fonstad; Lance A. Glasser; Ronald L. Rivest; MASSACHUSETTS INST OF TECH CAMBRIDGE
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| A better understanding of the limiting mechanisms in heterojunction transistors is leading to improved devices. Installation of an MBE system will allow production of the first samples in December 1983. Bipolar transistors have been fabricated on recrystallized silicon films for the first time. These are designed to study the properties of the film. A fully self-aligned JCMOS device has been fabricated with partial success. Another three-dimensional device structure, the staggered ... |
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Reports by Author
