| Parallel Adaptive Finite Element: Software for Semiconductor Device Simulation |
12 JAN 95 |
240 pages |
| Authors:
R. W. Dutton; K. H. Law; P. M. Pinsky; N. Aluru; STANFORD UNIV CA
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 | Parallel algorithms and fully functional application codes for 2D and 3D device analysis of semiconductor devices have been demonstrated. Advanced modeling based on a hydrodynamic formulation (HD) of the semiconductor transport equations and using a Galerkin Least Squares Finite Element Method (GLS-FEM) has demonstrated nearly ideal parallel performance for 2D MOS and Bipolar transistor applications across Intel and IBM machines. Parallelization of conventional drift-diffusion (DD) based device solvers has broken ... |
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| Computer Modeling of Complete IC Fabrication Process |
JAN 1984 |
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| Authors:
R. W. Dutton; STANFORD UNIV CA STANFORD ELECTRONICS LABS
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 | Process and device modeling, especially in two-dimensions, for the complete integrated circuit fabrication process is reported. New understanding of oxidation and diffusion effects in silicon are reported and new computer tools and techniques are discussed. Device simulation is coupled to process modeling and new results for both short- and narrow-channel devices are reported. Non-planar device simulators, both poisson and two-carrier capabilities, have been developed. New techniques have been developed for ... |
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| Kinetic Modeling and Measurement of Active Species Distributions during Dry Etching |
84 |
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| Authors:
K. S. Uhm; M. R. Kump; J. P. McVittie; R. W. Dutton; STANFORD UNIV CA CENTER FOR INTEGRATED SYSTEMS
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| A simple kinetic dry etching model accounting for generation, loss, and transport of the reactive and by-product species is developed. To demonstrate and evaluate the model, the etching of silicon using sulfur hexafluonde + oxygen + argon in the plasma etch mode is investigated. Keywords: Silicon. |
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| A Structured Design Methodology for VLSI Systems |
NOV 1983 |
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| Authors:
R. W. Dutton; STANFORD UNIV CA STANFORD ELECTRONICS LABS
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| New algorithms and tools for hierarchical design and verification of IC chips have been developed. The multi-level simulation capabilities of SABLE have been extended using the ADA language. Automatic synthesis of stick diagrams from net lists and subsequent pitch-constrained compaction of layout provide new capabilities for cell generation. New parallel algorithms for routing and design rule checking have been developed which are orders-of-magnitude faster than conventional approaches. Analytic models to ... |
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| Stanford Overview in VLSI Research |
JUL 1981 |
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| Authors:
R. W. Dutton; STANFORD UNIV CA CENTER FOR INTEGRATED SYSTEMS
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| Computer-Aided Engineering of Semiconductor Integrated Circuits. |
JUL 1980 |
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| Authors:
J. D. Meindl; R. W. Dutton; J. F. Gibbons; C. R. Helms; J. D. Plummer; STANFORD UNIV CALIF INTEGRATED CIRCUITS LAB
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| Economical procurement of small quantities of high performance custom integrated circuits for military systems is impeded by inadequate process, device and circuit models that handicap low cost computer aided design. The principal objective of this program is to formulate physical models of fabrication processes, devices and circuits to allow total computer-aided design of custom large-scale integrated circuits. The basic areas under investigation are (1) thermal oxidation, (2) ion implantation and ... |
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| Segregation of Arsenic to the Grain Boundaries in Polycrystalline Silicon, |
04 JAN 1980 |
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| Authors:
B. Swaminathan; E. Demoulin; T. W. Sigmon; R. W. Dutton; R. Reif; STANFORD UNIV CALIF INTEGRATED CIRCUITS LAB
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| Computer-Aided Engineering of Semiconductor Integrated Circuits |
JUL 1979 |
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| Authors:
J. D. Meindl; R. W. Dutton; J. F. Gibbons; J. D. Plummer; W. A. Tiller; STANFORD UNIV CA INTEGRATED CIRCUITS LAB
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| Economical procurement of small quantities of high performance custom integrated circuits for military systems is severely impeded by inadequate process, device and circuit models that handicap accurate computer-aided design at low cost. The salient objective of this program is to formulate physical models of fabrication processes, devices and circuits to allow total computer- aided design of custom large scale integrated circuit subsystems to reduce development cycle time and cost. The ... |
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| Computer Aided Engineering of Semiconductor Integrated Circuits. |
JUL 1978 |
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| Authors:
J. D. Meindl; K. C. Saraswat; R. W. Dutton; J. F. Gibbons; W. Tiller; STANFORD UNIV CALIF INTEGRATED CIRCUITS LAB
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| Economical procurement of small quantities of high performance custom integrated circuits for military systems is severely impeded by inadequate process, device and circuit models that handicap accurate computer-aided design at low cost. The salient objective of this program is to formulate physical models of fabrication processes, devices and circuits to allow total computer-aided design of custom large-scale integrated circuit subsystems to reduce development cycle time and cost. The basic areas ... |
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| Computer Aided Engineering of Semiconductor Integrated Circuits. |
APR 1978 |
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| Authors:
J. D. Meindl; K. C. Saraswat; R. W. Dutton; J. F. Gibbons; J. D. Plummer; STANFORD UNIV CALIF INTEGRATED CIRCUITS LAB
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| The objectives of this program are to remove the empiricism associated with the design and manufacturing of custom integrated circuits for military applications and to reduce the cost of these circuits by devising improved computer-aided engineering techniques. Efforts of research covered by this report are in the areas of (1) ion implantation and diffusion of dopants, (2) thermal oxidation, (3) chemical vapor deposition of silicon, and (4) device simulation and ... |
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| Oxidation and Epitaxy. |
MAY 1977 |
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| Authors:
R. W. Dutton; D. A. Antoniadis; J. D. Meindl; T. I. Kamins; K. C. Saraswat; STANFORD UNIV CALIF INTEGRATED CIRCUITS LAB
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| The first order process models for silicon epitaxy and oxidation are described. Epitaxial dopant inclusion, autodoping and transient effects are discussed, and experimental results are presented. Silicon orientation, surface doping, and ambient effects are considered for silicon-oxidation rates. (Author) |
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| MSINC - An MOS Simulator for Integrated Nonlinear Circuits with Modular Built-In Model. |
JUL 1974 |
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| Authors:
T. K. Young; R. W. Dutton; STANFORD UNIV CALIF STANFORD ELECTRONICS LABS
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| The paper describes MSINC, an MOS Simulator for Integrated Nonlinear Circuits. MSINC simulates the nonlinear dc and transient responses of MOS transistor circuits. The modular feature facilitates the alteration and replacement of semiconductor device models. Models other than MOS transistors can be implemented within the constraints of four external and two internal nodes. Only two subroutines need to be changed for model implementation - one for inputting the model specifications ... |
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