| PACT: Power Aware Compilation and Architectural Techniques |
AUG 2003 |
26 pages |
| Authors:
Majid Sarrafzadeh; Prithviraj Banerjee; Alok Choudhary; Andreas Moshovos; CALIFORNIA UNIV LOS ANGELES DEPT OF COMPUTER SCIENCE
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 | The goal of this project was to take DoD applications written in C and generate power and performance efficient code for systems utilizing the architectural power-aware techniques developed. The PACT project consisted of 3 research tasks: 1) Power-aware architectural approaches, 2) Power-aware compilation strategies, and 3) Power-aware CAD tools for power estimation and synthesis. As part of the power aware architecture research, we developed power aware techniques for on-chip buses, ... |
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| A MATLAB Compilation Environment for Adaptive Computing Systems |
JUN 2002 |
20 pages |
| Authors:
Prithviraj Banerjee; NORTHWESTERN UNIV EVANSTON IL
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| This report provides a brief summary of the research and development of a compiler for a mix of general purpose processors and adaptive computing processors from MATLAB. It incorporates a list of publications resulting from this research. |
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| VLSI CAD on Scalable High Performance Computing Platforms |
30 SEP 1998 |
13 pages |
| Authors:
Prithviraj Banerjee; ILLINOIS UNIV AT URBANA CENTER FOR RELIABLE AND HIGH- PERFORMANCE COMPUTING
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| In this research we have investigated parallel algorithms for placement, routing, layout verification and extraction, logic synthesis, test generation, and fault simulation, and behavioral simulation. The parallel algoritlnns have been designed such that they are portable across a range of parallel machines, including multiprocessor workstations, shared memory multiprocessors, message passing multiprocessors, and networks of workstations. The algorithms have been designed to run on top of the ProperCAD2 C++ library as ... |
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| A Framework for Exploiting Data and Functional Parallelism on Distributed Memory Multicomputers |
21 JUN 94 |
40 pages |
| Authors:
Shankar Ramaswamy; Sachin Sapatnekar; Prithviraj Banerjee; ILLINOIS UNIV AT URBANA CENTER FOR RELIABLE AND HIGH- PERFORMANCE COMPUTING
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| Recent research efforts have shown the benefits of integrating functional and data parallelism over using either pure data parallelism or pure functional parallelism. The work in this paper presents a theoretical framework for deciding on a good execution strategy for a given program based on the available functional and data parallelism in the program. The framework is based on assumptions about the form of computation and communication cost functions for ... |
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| Compile-Time Estimation of Communication Costs in Multicomputers |
22 MAY 91 |
24 pages |
| Authors:
Manish Gupta; Prithviraj Banerjee; ILLINOIS UNIV AT URBANA COORDINATED SCIENCE LAB
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| An important problem facing numerous research projects on parallelizing compilers for distributed memory machines is that of automatically determining a suitable data partitioning scheme for a program. Any strategy for automatic data partitioning needs a mechanism for estimating the performance of a program under a given partitioning scheme, the most crucial part of which involves determining the communication costs incurred by the program. In this paper, we describe a methodology ... |
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| Automatic Data Partitioning on Distributed Memory Multiprocessors |
OCT 90 |
39 pages |
| Authors:
Manish Gupta; Prithviraj Banerjee; ILLINOIS UNIV AT URBANA CENTER FOR RELIABLE AND HIGH- PERFORMANCE COMPUTING
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| An important problem facing numerous research projects on parallelizing compilers for distributed memory machines is that of automatically determining a suitable data partitioning scheme for a program. Most of the current projects leave this tedious problem almost entirely to the user. In this paper, we present a novel approach to the problem of automatic data partitioning. We introduce the notion of constraints on data distribution, and show how a parallelizing ... |
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