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Abstract:
Three-dimensional integration is an emerging chip fabrication technique in which multiple integrated circuit dies are joined using conductive posts. 3D integration offers several performance and security advantages, including extremely high bandwidth between the two dies and the ability to augment a processor with a separate die housing custom security features. This thesis performs a feasibility and requirements analysis of a data transformation coprocessor in a three-dimensional integrated circuit. We propose a novel coprocessor architecture in which one layer (control layer) houses application-specific coprocessors for cryptography and compression, which provide acceleration for applications running on a general-purpose processor in another layer (computational layer). The main application supported from our proposed 3DIC is the one that performs real-time trace collection, compresses the trace, and optionally encrypts the compressed trace, which protects the data from interception during transmission to permanent off-chip storage for offline program analysis. Although we are not building a hardware device for simulation we present the architecture for a 3D data transformation processor and a rationale for each of the key design decisions, including a compression study that determined the optimal compression algorithm for a specific set of traces.
| Limitations: |
 APPROVED FOR PUBLIC RELEASE |
| Description: |
Master's thesis |
| Pages: |
225 |
| Report Date: |
Mar 2012 |
| Report Number: |
A524065 |
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