Abstract: The advantages of using DSP chips for high-performance embedded signal processing applications have been demonstrated during the past decade. However, it is now apparent that even DSP chips can be overkill for some computations found in common embedded military applications. This project investigates the advantages of integrating configurable hardware together with a multiprocessor DSP/GPP platform. The computational engine of the configurable hardware used in this project was comprised of FPGA chips. A primary goal of our project was to demonstrate that for given computational loads--associated with instances of embedded radar signal processing applications-the total size, weight, and power (SWAP) could be reduced by integrating FPGA-based components as part of the embedded computational platform.
| Limitations: |
 APPROVED FOR PUBLIC RELEASE |
| Description: |
Final technical rept. Jul 1997-Oct 2001 |
| Pages: |
142 |
| Report Date: |
SEP 2003 |
| Contract Number: |
F30602-97-2-0297, DARPA ORDER- |
| Report Number: |
A186814 |
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